17 Dec, 2010
1 commit
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The on-board NMI switch is routed through and mangled by the FPGA prior
to its delivery to the NMI pin, so add some glue for the various
configuration options. The default is to unmask it and enable all input
sources.Signed-off-by: Paul Mundt
15 Oct, 2010
1 commit
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This ties in the 2KiB of FPGA SRAM in to the generic SRAM pool.
Signed-off-by: Paul Mundt
14 Oct, 2010
2 commits
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The SDK7786 FPGA has secondary control over the PCIe clocks, specifically
relating to the slots and oscillator. This ties the FPGA clocks in to the
clock framework and balances the refcounting similar to how the primary
on-chip clocks are managed. While the on-chip clocks are per-port, the
FPGA clock enable/disable is global for the entire block.Signed-off-by: Paul Mundt
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SDK7786 supports connecting either slot3 or 4 to the same PCIe port by
way of FPGA muxing. By default the vertical slot 3 on the baseboard is
enabled, so this adds in a command line option for forcibly enabling the
slot 4 edge connector.If nothing has been specified on the command line, we fall back to
reading the resistor values for card presence to figure out where to
route the port to.Signed-off-by: Paul Mundt
19 Apr, 2010
1 commit
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This wires up power-off support for the SDK7786 board.
Signed-off-by: Paul Mundt
20 Jan, 2010
3 commits
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This implements dynamic probing for the system FPGA. The system reset
controller contains a fixed magic read word in order to identify the
FPGA. This just utilizes a simple loop that scans across all of the fixed
physical areas (area 0 through area 6) to locate the FPGA.The FPGA also contains register information detailing the area mappings
and chip select settings for all of the other blocks, so this needs to be
done before we can set up anything else.Signed-off-by: Paul Mundt
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This moves out the FPGA IRQ controller setup code to its own file, in
preparation for switching off of IRL mode and having it provide its own
irq_chip.Signed-off-by: Paul Mundt
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This does a bit of refactoring of the FPGA management code. The primary
FPGA initialization is moved out to its own file in preparation for
implementing some of the more complex capabilities, a complete set of
register definitions is provided, and all of the existing users in the
board code are moved over to use the new interface instead of setting up
overlapping mappings. This also corrects the FPGA size, which previously
was chomped off at the SDIF control register.Signed-off-by: Paul Mundt