06 Mar, 2019
1 commit
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Fix lvds-pwm usage, it needs to be under vehicle_rpmsg_m4 node for
android auto.Signed-off-by: Peng Fan
(cherry picked from commit 31db2776c4cf4b27417c57f3c7c013085cee1528)
05 Mar, 2019
13 commits
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Change the default HDMI clocks to 800 MHz for DPLL, 200 MHz for
core, and 100MHz for bus.Signed-off-by: Oliver Brown
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Need to change the default HDMI TX clocks to 800 MHz for DPLL and 100 MHz
for bus.Signed-off-by: Oliver Brown
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I2c_lock_bus function in i2c-core-base will not stop the transfer to
different devices on different buses at the same time.Since the multiple rpmsg i2c buses share one rpmsg channel, so it has to
add mutex to protect rpmsg resource accessing.Signed-off-by: Clark Wang
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For QM and QXP, the PHY_REF clock was default ON on SCFW so it was not
handled by driver. Since now this clock is OFF in SCFW, it can be
correctly handled by kernel driver.
Now, the PHY_REF clock rate is set by the nwl-dsi bridge driver,
depending on the display mode used.
In this driver, the PIXEL and BYPASS clocks rates were set to the same
rate as the PHY_REF, but their rates need to be set to current display
mode clock.
Also, the order of the clocks matters, so make sure the BYPASS is
enabled before the PIXEL clock.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Until now, the DSI PHY_REF clock was by default ON in SCFW, which made
this clock unusable in kernel, therefore, this clock was set as
CLK_DUMMY in DSI device nodes.
Sinnce this clock was set to OFF in SCFW, now it can be used from
kernel, so add it to device nodes so that the driver can use it
properly.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
The DSI PHY_REF clock for the second DSI instance was missing from the
clock driver, so add it now.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
Add the missing clocks for the DSI PHY_REF:
IMX8QM_MIPI0_DSI_PHY_CLK and IMX8QM_MIPI1_DSI_PHY_CLK.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
DP driver will hang if driver initialized in un-linked status.
Add DP link status check to avoid system hang.Signed-off-by: Sandor Yu
(cherry picked from commit 3626e1b4fe9c042705e72de3ac40d7e31193370c) -
DPCD read function should return actual read size.
msg->size is the requested read size
so replaced it with read_resp.size.Signed-off-by: Sandor Yu
(cherry picked from commit 7ae79233dd2df543f92a30d5b466295666008408) -
AVI info frame will failed work when hdmi in 4kp30/24/25.
It is caused by the data is overwritten by hdmi vendor info frame.
Change the hdmi vendor info frame to different address.Signed-off-by: Sandor Yu
(cherry picked from commit 399072542cbdab2e1d758b34a152ba71be5b8d17) -
hdmi_vendor_info function only valid for HDMI1.4 4K video mode,
remove return value check.
Remove dumplicate hdmi_avi_info_set function call.Signed-off-by: Sandor Yu
(cherry picked from commit 3cc51bd99d5ab7514c36f217b54f91136aa30bef) -
Add max tmds clock check in deep color mode.
Make sure tmds clock is not excess hdmi sink capability.Signed-off-by: Sandor Yu
(cherry picked from commit 672768a727f35512919d6b9ccc124d26395c5a65)
04 Mar, 2019
2 commits
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When system resume from VLPS mode, DDR IO must be restored
before mmdc out of the self-fresh mode.Signed-off-by: Jacky Bai
Tested-by: Anson Huang
(cherry picked from commit 7dec20bcb6633c7feee1eb32a5d81356075a61f7) -
H264 frame
H264 may re-order the sequence of frame. report the sequence through
v4l2_buffer->sequence.
copy the timestamp of yuv frame to h264 frameSigned-off-by: ming_qian
02 Mar, 2019
1 commit
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Commit b311ef1d549b ("MLK-20989: Driver: lpuart: reset registers
before enable lpuart") breaks early console function, and the
commit already was reverted. The reworked patch is to fix the
issue correctly.This patch has been tested on i.MX8QM/QXP.
change log:
V1 -> V2:
1. Remove lock, since there is no race condition.Suggested-by: Peng Fan
Signed-off-by: Flynn xu
01 Mar, 2019
6 commits
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These CAN related regulators will be handled when kernel boots. However,
these regulators which aren't used by any devices will be disabled by the
regulator framework. So, the pins in these regulators will be non-active
status. This causes the CAN module cannot be used in M4 side.So, disable these regualtors for 8QM/QXP, and let M4 handles these.
Suggested-by: Fugang Duan
Signed-off-by: Clark Wang -
1. specify feed_mod when start
2. modify firmware debug log
extend 'vpu_frmdgb_ena' for multi-instance
update structure MediaIPFW_Video_DbgLogDesc
add one parameter to config 'uDecStatusLogLevel'
3. update structure MediaIPFW_Video_SeqInfo to get Color Aspect
information from firmware in furture
4. add verifation before handle vb2_buffer address
5. add verifation before handle ctx->dbglog_dir
6. delete '#ifdecf COREPLAY_API' in mediasys_types.hSigned-off-by: Shijie Qin
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If timer is deleted in suspend, when the suspend is resumed
by pressing the power key, there will be no timer until the buffer
empty, and the hw_ptr will not be updated.So the timer should not be removed at suspend.
Signed-off-by: Shengjiu Wang
(cherry picked from commit 9a17ce36ecef46ea5ec88d4b89b117abe8eebf8f) -
In LPA, we use the timer to simulate the interrupt, if the period time
is 1s, the timer is 500ms, which means the interrupt is more frequent
than actual.With pause ALSA will update the hw_ptr_jiffies, because the interrupt
is more frequent, so sometimes in snd_pcm_update_hw_ptr0, the condition
delta > new_hw_ptr will be true, then the new_hw_ptr will be added whole
buffer_size, which cause the whole buffer be flushed.if (in_interrupt) {
/* we know that one period was processed */
/* delta = "expected next hw_ptr" for in_interrupt != 0 */
delta = runtime->hw_ptr_interrupt + runtime->period_size;
if (delta > new_hw_ptr) {
/* check for double acknowledged interrupts */
hdelta = curr_jiffies - runtime->hw_ptr_jiffies;
if (hdelta > runtime->hw_ptr_buffer_jiffies/2 + 1) {
hw_base += runtime->buffer_size;
if (hw_base >= runtime->boundary) {
hw_base = 0;
crossed_boundary++;
}
new_hw_ptr = hw_base + pos;
goto __delta;
}
}
}So even we use the timer to simulate the interrupt, the timer should
be same as the period time, otherwise will cause issue.Signed-off-by: Shengjiu Wang
(cherry picked from commit 9a9af932118774083119dba72c5c6133852ba926) -
Passthrough lvds pwm, otherwise dom0 will panic when reboot if
domu started and shutdown, because LVDS_1_PWM_0 is assigned
to domu and when domu shutdown, the resource will be powered
off, however dom0 still think it is powered on.since lvds1_pwm is expected for domu, so let's passthrough it.
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
(cherry picked from commit abb243aba12a6649fad8114e298ff075b0a8399d) -
Move the emmc/lpuart/sdcard/sensor/spi-slave testing features
from EVK to EVKB board.Signed-off-by: Shenwei Wang
Reviewed-by: Frank Li
28 Feb, 2019
2 commits
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The IPG clock is introduced for i2c0 and i2c2 nodes in order to do
properly clock gating/ungating for i2c0 and i2c2.
'ipg' clock drives the access to the device iomapped registers,
so with this patch we are now able to read I2C registers.Signed-off-by: Stoica Cosmin-Stefan
Reviewed-by: Daniel Baluta
Reviewed-by: Fugang Duan -
Before calling devm_request_irq to register a sport->port.irq,
the lpuart register might not be in a correct status.When LPUART Control register is not it's reset value, such as 0xbc0700,
this indicate there are unhandled irqs, thus, irq handler lpuart32_int
will be triggered right after devm_request_irq, and this happens
before uart_add_one_port which would init sport->port.state, then
lpuart32_int will call lpuart_txint, and lpuart_txint will access
sport->port.state->xmit, but at this point, sport->port.state is
not init yet, then, kernel panic.This can be reproduced with jailhouse support dual Linux on i.MX8.
When the 2nd Linux is running, and echo a message repeatedly,
the 1st Linux force the 2nd Linux to destroy without any notification
to the 2nd Linux. Then boot the 2nd Linux again, the issue could
be reproduced.Kernel dump:
[ 0.795118] fsl-lpuart 5a060000.serial: failed to get alias id, errno -19
[ 0.801963] Unable to handle kernel NULL pointer dereference at virtual address 00000170
[ 0.809570] Mem abort info:
[ 0.812241] Exception class = DABT (current EL), IL = 32 bits
[ 0.817908] SET = 0, FnV = 0
[ 0.820829] EA = 0, S1PTW = 0
[ 0.823831] Data abort info:
[ 0.826584] ISV = 0, ISS = 0x00000004
[ 0.830254] CM = 0, WnR = 0
[ 0.833090] [0000000000000170] user address but active_mm is swapper
[ 0.839180] Internal error: Oops: 96000004 [#1] PREEMPT SMP
[ 0.844516] Modules linked in:
[ 0.847440] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.98-05833-gc561a05e6ee7 #209
[ 0.855024] Hardware name: Freescale i.MX8QXP MEK (DT)
[ 0.859946] task: ffff800024000000 task.stack: ffff000008068000
[ 0.865628] PC is at lpuart_txint.isra.5+0x6c/0x388
[ 0.870288] LR is at lpuart_txint.isra.5+0x1c/0x388
[ 0.874957] pc : [] lr : [] pstate: 600001c5
[ 0.882045] sp : ffff000008003de0
[ 0.885212] x29: ffff000008003de0 x28: ffff800024000000
[ 0.890300] x27: 0000000000000000 x26: ffff0000092263e8
[ 0.895387] x25: ffff0000096d6c43 x24: ffff80002423a600
[ 0.900474] x23: 0000000000000009 x22: 00000000000001c0
[ 0.905562] x21: 0000000000000200 x20: 0000000000c00000
[ 0.910649] x19: ffff8000246bb018 x18: 0000000000000001
[ 0.915736] x17: 0000000000000001 x16: 0000000000000019
[ 0.920824] x15: ffffffffffffffff x14: ffffffffffffffff
[ 0.925911] x13: 0000000000000038 x12: 0101010101010101
[ 0.930999] x11: 0000000000000020 x10: 0000000000000040
[ 0.936086] x9 : ffff000009552fe8 x8 : ffff800026000248
[ 0.941174] x7 : ffff800026000270 x6 : 0000000000000000
[ 0.946261] x5 : ffff800026000248 x4 : 0000000000000000
[ 0.951348] x3 : 00000000000001c0 x2 : 0000000000000000
[ 0.956436] x1 : 0000000000000003 x0 : 0000000000000000
[ 0.961526] Process swapper/0 (pid: 1, stack limit = 0xffff000008068000)
[ 0.967947] Call trace:
[ 0.970286] Exception stack(0xffff000008003ca0 to 0xffff000008003de0)
[ 0.976461] 3ca0: 0000000000000000 0000000000000003 0000000000000000 00000000000001c0
[ 0.983962] 3cc0: 0000000000000000 ffff800026000248 0000000000000000 ffff800026000270
[ 0.991470] 3ce0: ffff800026000248 ffff000009552fe8 0000000000000040 0000000000000020
[ 0.998975] 3d00: 0101010101010101 0000000000000038 ffffffffffffffff ffffffffffffffff
[ 1.006480] 3d20: 0000000000000019 0000000000000001 0000000000000001 ffff8000246bb018
[ 1.013986] 3d40: 0000000000c00000 0000000000000200 00000000000001c0 0000000000000009
[ 1.021493] 3d60: ffff80002423a600 ffff0000096d6c43 ffff0000092263e8 0000000000000000
[ 1.029001] 3d80: ffff800024000000 ffff000008003de0 ffff0000086398d4 ffff000008003de0
[ 1.036505] 3da0: ffff000008639924 00000000600001c5 ffff8000245eec00 ffff800024486000
[ 1.044013] 3dc0: 0000ffffffffffff ffff000009555e80 ffff000008003de0 ffff000008639924
[ 1.051520] [] lpuart_txint.isra.5+0x6c/0x388
[ 1.057188] [] lpuart32_int+0x2a8/0x680
[ 1.062363] [] __handle_irq_event_percpu+0x5c/0x148
[ 1.068530] [] handle_irq_event_percpu+0x1c/0x58
[ 1.074451] [] handle_irq_event+0x48/0x78
[ 1.079792] [] handle_fasteoi_irq+0xa8/0x180
[ 1.085379] [] generic_handle_irq+0x24/0x38
[ 1.090881] [] __handle_domain_irq+0x5c/0xb8
[ 1.096469] [] gic_handle_irq+0x78/0x174
[ 1.101722] Exception stack(0xffff00000806b980 to 0xffff00000806bac0)
[ 1.107895] b980: ffff80002423a6a4 0000000000000000 0000000000000005 0000000000000000
[ 1.115400] b9a0: 0000000000000004 0000000000000003 000000000000003f 0000000000000000
[ 1.122909] b9c0: ffff80002444de80 0000000000000000 0000000000000040 0000000000000020
[ 1.130413] b9e0: 0101010101010101 0000000000000038 ffffffffffffffff ffffffffffffffff
[ 1.137920] ba00: 0000000000000019 0000000000000001 0000000000000001 ffff80002423a600
[ 1.145425] ba20: ffff80002444de00 0000000000000009 ffff80002423a628 0000000000000000
[ 1.152931] ba40: ffff80002423a758 ffff80002423a6a4 0000000000000000 0000000000000000
[ 1.160437] ba60: ffff00000951aae8 ffff00000806bac0 ffff00000811dcb4 ffff00000806bac0
[ 1.167943] ba80: ffff000008dd6ff0 0000000040000005 ffff00000806bad0 ffff00000811dec8
[ 1.175451] baa0: ffffffffffffffff ffff80002444de00 ffff00000806bac0 ffff000008dd6ff0
[ 1.182956] [] el1_irq+0xb0/0x124
[ 1.187629] [] _raw_spin_unlock_irqrestore+0x18/0x48
[ 1.193882] [] __setup_irq+0x524/0x7c8
[ 1.198968] [] request_threaded_irq+0xe4/0x1a0
[ 1.204722] [] devm_request_threaded_irq+0x7c/0xf8
[ 1.210811] [] lpuart_probe+0x364/0x580
[ 1.215984] [] platform_drv_probe+0x58/0xb8
[ 1.221489] [] driver_probe_device+0x210/0x2d0
[ 1.227240] [] __driver_attach+0xbc/0xc0
[ 1.232497] [] bus_for_each_dev+0x4c/0x98
[ 1.237834] [] driver_attach+0x20/0x28
[ 1.242919] [] bus_add_driver+0x1b8/0x228
[ 1.248255] [] driver_register+0x60/0xf8
[ 1.253510] [] __platform_driver_register+0x40/0x48
[ 1.259687] [] lpuart_serial_init+0x38/0x5c
[ 1.265189] [] do_one_initcall+0x38/0x128
[ 1.270527] [] kernel_init_freeable+0x188/0x22c
[ 1.276366] [] kernel_init+0x10/0x108
[ 1.281368] [] ret_from_fork+0x10/0x18
[ 1.286458] Code: 14000022 910802b5 39428a61 71000c3f (296e0aa3)
[ 1.292305] ---[ end trace 3559accd3c908fe3 ]---
[ 1.296713] Kernel panic - not syncing: Fatal exception in interrupt
[ 1.302798] SMP: stopping secondary CPUs
[ 1.306557] Kernel Offset: disabled
[ 1.309889] CPU features: 0x0802008
[ 1.313223] Memory Limit: none
[ 1.316146] ---[ end Kernel panic - not syncing: Fatal exception in interruptSuggested-by: Peng Fan
Signed-off-by: Flynn xu
Acked-by: Fugang Duan
(cherry picked from commit b311ef1d549bedf0459b9f6c0b9fd82587c20d70)
27 Feb, 2019
3 commits
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Update SCFW APIs to SCFW commit:
e7a99eb96207 ("SCF-351: Add API to change boot parms.")Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
(cherry picked from commit 974c09d8389989fc75df161d78e932032176ce22) -
This reverts commit b311ef1d549bedf0459b9f6c0b9fd82587c20d70.
This patch works on jailhouse inmate linux and domu linux,
but breaks non-virtualization environment, so remove this patch.(cherry picked from commit a69c26be1f65efa2195e5ca499ae0b148db23d3b)
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Switch to use rpmsg i2c to support android auto, because
android auto change to use rpmsg i2c.
Also add the alias node to let m4 could use it successfully, because
M4 side use the alias id as the BUSID.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu
26 Feb, 2019
6 commits
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The resources are wrongly added.
Signed-off-by: Peng Fan
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Cleanup the resources that not could be set SID and remove the UNUSED
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
Update domu car dts according to android auto changes.
Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
When resources are owned by M41, we need to handle that correctly in
xen.Also drop power doamins for xen,shared gpio, xen will power up the gpio.
gpio1 is owned by M41, so we also need to check its power status in xen.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
CM41 runs before CortexA, we should not use smmu to restrict it, because
smmu is owned by xen. Also remove MU_13/12 which is wrongly added
before.Signed-off-by: Peng Fan
Reviewed-by: Flynn xu -
reduce the time that open operation spent,
allocate the buffer when neededSigned-off-by: ming_qian
25 Feb, 2019
3 commits
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mode
Can't set mode like loopback,listen-only and so on due to wrong setting when
enable ISO-FD mode.Signed-off-by: Joakim Zhang
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kernel process(with zero pid) has no mdl mapping,
skip kernel process to avoid invalid mdl access.also remove memory barrier to avoid rcu issue.
Signed-off-by: Xianzhong
(cherry picked from commit 5ced43c64b88fb4c6106fa295dc7e55a1a5c7bef) -
The hdmi_drm_infoframe_pack() was wrongly packing the HDR metadata. It
was setting the x display primaries followed by the y display primaries.
Instead, in the specifications, each x display primary should be
followed by the corresponding y display primary.Also, byte 8 of the frame payload was being skipped. Fixed that too.
Signed-off-by: Laurentiu Palcu
Reported-by: Jared Hu
23 Feb, 2019
3 commits
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change the flexspi pad settings to pull_up and drive_low to avoid
overshoot.Signed-off-by: Han Xu
(cherry picked from commit f55654688059a337490915cd6f652d0585597f3d) -
Add delay cell support for fspi to set calibrated value to DLL register
for different clock frequency.Signed-off-by: Han Xu
(cherry picked from commit 5b608b98697668bd11563febba89bd0eea1c1b26) -
Several code changes to improve the i.MX8MM fspi performance.
- Implemented the SFDP lut to get the correct chip information
- Changed the default read mode from normal read to Quad DDR
- Enabled the AHB prefetch after chip probed
- Limited the highest clock rate for iMX8MMSigned-off-by: Han Xu
(cherry picked from commit c8dfe6ab108909a2e5bbc0ec11f3a24ad5b5844d)
