17 Jan, 2008

6 commits


11 Jan, 2008

1 commit


09 Jan, 2008

5 commits


08 Jan, 2008

3 commits


05 Jan, 2008

1 commit


03 Jan, 2008

1 commit


31 Dec, 2007

2 commits


29 Dec, 2007

1 commit


28 Dec, 2007

2 commits

  • By default the OpenPIC on PWRficient will bias to one core (since that
    will improve changes of the other core being able to stay idle/powered
    down). However, this conflicts with most irq load balancing schemes,
    since setting an interrupt to be delivered to either core doesn't really
    result in the load being shared. It also doesn't work well with the
    soft irq disable feature of PPC, since EE will stay on until the first
    interrupt is taken while soft disabled.

    Set the gconf0 config bit that enables even distribution of interrupts
    among the two cores.

    Signed-off-by: Olof Johansson

    Olof Johansson
     
  • Some PWRficient-based boards have a NMI button that's wired up to a GPIO
    as interrupt source. By configuring the openpic accordingly, these get
    delivered as a machine check with high priority, instead of as an external
    interrupt.

    The device tree contains a property "nmi-source" in the openpic node
    for these systems, and it's the (hwirq) source for the input.

    Also, for these interrupts, the IACK is read from another register than
    the regular (MCACK instead), but they are EOI'd as usual. So implement
    said function for the mpic driver.

    Finally, move a couple of external function defines to include/ instead
    of local under sysdev. Being able to mask/unmask and eoi directly saves
    us from setting up a dummy irq handler that will never be called.

    Signed-off-by: Olof Johansson

    Olof Johansson
     

25 Dec, 2007

3 commits


24 Dec, 2007

15 commits