08 Jun, 2017
40 commits
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In order to pass the pcie gen2 compliance tests on imx6qp
sd revb board, add one standalone imx6qp sd ldo pcie dtb
- disalbe fec/sata, because that the fec/sata can't work
when pll6 is in bypass mode.
NOTE: Bypass mode of pll6 is mandatory required when
external oscillator is used as pcie ref clk.Signed-off-by: Richard Zhu
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In order to pass the pcie gen2 electronic compliance
tests, the external oscillator is manatory required.
Enable pcie external osc support on imx6qp platformsSigned-off-by: Richard Zhu
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BCMDHD_SDIO needs to be tristate for the correct dependency
of MMC core subsystem.
And the old driver buildin mode is static defined by DRIVER_TYPE.
Fix it to depend on CONFIG_BCMDHD_SDIO.Signed-off-by: Dong Aisheng
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Due to the errata ERR010450 limit, this patch change the imx6ull
usdhc root clock to 132MHz in soc related dts file, remove all
the root clock setting in board dts file, after this patch,
SDR104/HS200 work at 132MHz, DDR50/DDR52 work at 33MHz.Signed-off-by: Haibo Chen
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i.MX6ULL has errata ERR010450, which says due to SOC I/O timing
limit, eMMC HS200 and SD/SDIO 3.0 SDR104 at 1.8v can only work
below or equal to 150MHz. And eMMC DDR52 and SD/SDIO DDR50 at
1.8v can only work below or equal to 45MHz.This patch add this limit for imx6ull.
Signed-off-by: Haibo Chen
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For imx6ul PHY, when the system enters suspend, its 1p1 is off by default,
that may cause the PHY get inaccurate USB DP/DM value. If the USB wakeup
is enabled at this time, the unexpected wakeup may occur when the system
enters suspend.In this patch, when the vbus is there, we enable weak 1p1 during the PHY
suspend API, in that case, the USB DP/DM will be accurate for USB PHY,
then unexpected usb wakeup will not be occurred, especially for the USB
charger is connected scenario. The user needs to enable PHY wakeup for
USB wakeup function using below setting.echo enabled > /sys/devices/platform/soc/2000000.aips-bus/20c9000.usbphy
/power/wakeupCc: Shaojun Wang
Cc: Anson Huang
Signed-off-by: Peter Chen -
Error: arch/arm/boot/dts/imx6q-pop-arm2.dts:61.26-27 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:293: recipe for target
'arch/arm/boot/dts/imx6q-pop-arm2.dtb' failed
make[1]: *** [arch/arm/boot/dts/imx6q-pop-arm2.dtb] Error 1
arch/arm/Makefile:327: recipe for target 'dtbs' failed
make: *** [dtbs] Error 2
make: *** Waiting for unfinished jobs....Include gpio dt-bindings header file to resolve GPIO_ACTIVE_HIGH macro
Signed-off-by: Haibo Chen
Signed-off-by: Adrian Alonso -
Add power on gpio key for wake up source from suspend
Signed-off-by: Adrian Alonso
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Set soc arm as shared, arm_reg and soc_reg share the same
voltage rail source on imx6q pop arm2 target platformSigned-off-by: Adrian Alonso
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Enable egalax_ts touch screen support for imx6q pop arm2
target platform.Signed-off-by: Adrian Alonso
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Enable lvds channel 0 display support for imx6q pop arm2
validation target board.Signed-off-by: Adrian Alonso
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Enable hdmi display support for imx6q pop arm2 validation
target board.Signed-off-by: Adrian Alonso
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Simplify system root clock sources, only use pll2_pfd2 and osc
for system clocks, when busfreq request high bus mode or audio bus
mode only update dividers to achieve operating frequencies from
same source (pll2_pfd2).Bus freq mode (400M) (100M) (24Mhz)
mmdc_ch0_clk_root @396MHz @99MHz @24Mhz
axi_clk_root @198MHz @49.5MHz @24Mhz
ahb_clk_root @132MHz @49.5Mhz @24Mhz
ipg_clk_root @66MHz @24.75Mhz @12MhzSigned-off-by: Adrian Alonso
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On imx6qp sabresd rev b board, there is a standalone
external oscilator, used to provided the clks for
imx6qp pcie.Add one regulator into pcie node, let the ext osc work.
Signed-off-by: Richard Zhu
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On imx6qp sabresd rev b board, there is a standalone
external oscilator, used to provided the clks for
imx6qp pcie.
Add one regulator into pcie node, let the ext osc work.Signed-off-by: Richard Zhu
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Enable OOB feature for MX6Q/DL SDB, MX6SL EVK, MX6SX SDB, MX7D SDB boards.
NOTE: The performance optimization option CONFIG_BCM4339 is disabled
by default due to a WiFi driver issue that it breaks MX6SL EVK.If user want to test performance on the above platforms (except MX6SL EVK),
CONFIG_BCM4339 has to be enabled manually.Signed-off-by: Dong Aisheng
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The patch is delivered by Cypress to add OOB switch interface
and a P2P stability fix.Whether to enable OOB is controlled by the gpios property under
bcmdhd_wlan_0 node.
e.g.
bcmdhd_wlan_0: bcmdhd_wlan@0 {
compatible = "android,bcmdhd_wlan";
gpios = ; /* WL_HOST_WAKE */
wlreg_on-supply = ;
};If valid gpios property found, then driver will consider to use
OOB feature.Signed-off-by: Dong Aisheng
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For Mega/Mix enabled SoCs like MX7D and MX6SX, uSDHC will lost power in
LP mode no matter whether the MMC_KEEP_POWER flag is set or not.
This may cause state misalign between kernel and HW, especially for
SDIO3.0 WiFi cards.
e.g. SDIO WiFi driver usually will keep power during system suspend.
And after resume, no card re-enumeration called.
But the tuning state is lost due to Mega/Mix.
Then CRC error may happen during next data transfer.So we should always fire a mmc_retune_needed() for such type SoC
to tell MMC core retuning is needed for next data transfer.Signed-off-by: Dong Aisheng
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On i.MX6QP SabreSD board, AVDD supply is changed to VGEN6.
Signed-off-by: Robby Cai
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On i.MX6ULL, when the CPU freq is running at 198MHz or 396MHz, the system will
enter low bus mode if no device need high bus mode. The first time the system
entering low bus mode, CPU freq will be set to 24MHz, if cpufreq change the CPU
freq from 198MHz(396MHz) to 396MHz(198MHz), the CPU freq will be set to 198MHz or
396 MHz. At this time, if the CPU enter low power idle, system will hang.Signed-off-by: Bai Ping
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On i.MX6ULL, it has a low power run mode support, so we add this porperty
for this mode.Signed-off-by: Bai Ping
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Since the eink panel will not be re-initialized after exit DSM(deep sleep mode),
it will depend on the last update content so we need keep the associated working
buffer content during DSM. The patch moves the initialization of working buffer
to probe() function and ensure it's just be initialized once and thus its
content will be kept.The patch shall fix the following issue:
The codes as follows in unit test for clearing screen does not take effect
when enter/exit DSM.---
printf("Blank screen\n");
memset(fb, 0xFE, screen_info.xres_virtual*screen_info.yres*screen_info.bits_per_pixel/8);
update_to_display(0, 0, screen_info.xres, screen_info.yres,
wave_mode, TRUE, 0);
---Signed-off-by: Robby Cai
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The imx6ul/imx6ull iomuxc syscon is compatible to imx6q,
so let's add compatible string 'fsl,imx6q-iomuxc-gpr'
for imx6ul/imx6ull iomuxc syscon node.Without this compatible string, GINT bit will NOT be
set and workaround for ERR007265 is NOT reliable.Signed-off-by: Anson Huang
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When VPU runs at 396MHz, VDDSOC_CAP's voltage
should be set to 1.275V for all set-points,
add VPU clock rate check to support this case.Signed-off-by: Anson Huang
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When i.MX6QP with speed grading fuse blown to 1.2GHz,
VPU should run at 396MHz, add this support.Signed-off-by: Anson Huang
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When VPU is running at 396MHz, need to increase
VDDSOC_CAP voltage for all cpu set-points, so add
vpu clock node for cpufreq driver.Signed-off-by: Anson Huang
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On i,MX6SL, no NUM and DENUM register, so this PLL should not
be registered as IMX_PLLV3_GENERIC type PLL, it should be
registered as IMX_PLLV3_SYSV2.Signed-off-by: Bai Ping
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Added clock enable and disable to the probe and remove functions
where appropriate.Signed-off-by: Dan Douglass
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According the the latest datasheet, we updated the lowest
OPP to 198MHz. So we need to update the cpufreq code to fix
the syttem hang issue when run 'cpufreq-info' in low bus mode
on i.MX6ULL.Signed-off-by: Bai Ping
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According to the latest datasheet(Rev. 0,09/2016), update the
setpoints of i.MX6ULL. we add 25mV margin to cover IR drop
and board tolerance.LDO enable:
Freq VDD_SOC VDD_ARM
528MHz 1.175V 1.175V
396MHz 1.175V 1.025V
198MHz 1.175V 0.95VLDO bypass
Freq VDD_SOC VDD_ARM
528MHz 1.175V 1.175V
396Mhz 1.175V 1.175V
198MHz 1.175V 1.175VSigned-off-by: Bai Ping
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cs42xx8 is a 24 bit device, the maximum supported bit is 24bit.
So remove the S32_LE from the supported list.Signed-off-by: Shengjiu Wang
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Enable DCP in imx6ull.dtsi
Signed-off-by: Dan Douglass
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Enable DCP driver in imx_v7_defconfig
Signed-off-by: Dan Douglass
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Enable DCP support for imx6 series.
Signed-off-by: Dan Douglass
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Enable hardware RNG in imx6ull.dtsi
Signed-off-by: Dan Douglass
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Enable the RNG driver in imx_v7_defconfig
Signed-off-by: Dan Douglass
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Signed-off-by: Dong Aisheng
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Add DTS file imx6ull-9x9-evk.dts which is originated from i.MX6UL EVK with
some changes:
1. Include imx6ull.dtsi as base
2. sim2 is removed.
3. Move GPIO5 pins setting to iomuxc-snvs
4. Enable CSI and ov5640Signed-off-by: Ye Li
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running following vte stress test will meet "mx6s-csi 21c4000.csi: mx6s_csi_irq_handler Rx fifo overflow"
and cannot be stopped to capture again.i=0; while [ $i -lt 3000 ];do v4l2_capture_emma -D /dev/video1 -C 2 -M 0 -J 30,4 -W 640 -H 480;i=`expr $i + 1`;done
This patch adds the same handling as BIT_HRESP_ERR_INT for BIT_RFF_OR_INT
(RxFiFo OverFlow) to reset CSI as a recovery.Signed-off-by: Robby Cai
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As i.MX6's PLL2 also support a fractional-N
synthesizer, so we need to consider the NUM
and DENOM's value to get a correct rate, as
fraction may be used in some cases.Remove round_rate and set_rate for PLL2, as
it is NOT allowed to be changed in kernel
dynamically, otherwise, PFDs and DDR may NOT
work normally, it normally should be changed
in u-boot before DDR is enabled.Signed-off-by: Anson Huang