10 Mar, 2009
1 commit
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* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (29 commits)
p54: fix race condition in memory management
cfg80211: test before subtraction on unsigned
iwlwifi: fix error flow in iwl*_pci_probe
rt2x00 : more devices to rt73usb.c
rt2x00 : more devices to rt2500usb.c
bonding: Fix device passed into ->ndo_neigh_setup().
vlan: Fix vlan-in-vlan crashes.
net: Fix missing dev->neigh_setup in register_netdevice().
tmspci: fix request_irq race
pkt_sched: act_police: Fix a rate estimator test.
tg3: Fix 5906 link problems
SCTP: change sctp_ctl_sock_init() to try IPv4 if IPv6 fails
IPv6: add "disable" module parameter support to ipv6.ko
sungem: another error printed one too early
aoe: error printed 1 too early
net pcmcia: worklimit reaches -1
net: more timeouts that reach -1
net: fix tokenring license
dm9601: new vendor/product IDs
netlink: invert error code in netlink_set_err()
...
05 Mar, 2009
3 commits
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Signed-off-by: Stanislaw Gruszka
Cc: Andrew Victor
Acked-by: Sergei Shtylyov
Acked-by: Andrew Victor
Signed-off-by: Bartlomiej Zolnierkiewicz -
This is IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory
Controller with Compact Flash True IDE Mode logic.Driver have to switch 8/16 bit bus width when accessing Task Tile or Data
Register. Moreover some extra things need to be done when setting PIO mode.
Only PIO mode is used, hardware have no DMA support. If interrupt line is
connected through GPIO extra quirk is needed to cope with fake interrupts.Signed-off-by: Stanislaw Gruszka
Cc: Andrew Victor
Acked-by: Sergei Shtylyov
Signed-off-by: Bartlomiej Zolnierkiewicz
04 Mar, 2009
1 commit
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* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] fix lots of ARM __devexit sillyness
[ARM] 5417/1: Set the correct cacheid for ARMv6 CPUs with ARMv7 style MMU
[ARM] 5416/1: Use unused address in v6_early_abort
[ARM] 5411/1: S3C64XX: Fix EINT unmask
[ARM] at91: fix for Atmel AT91 powersaving
[ARM] RiscPC: Fix etherh oops
03 Mar, 2009
3 commits
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The cacheid_init() function assumes that if cpu_architecture() returns
7, the caches are VIPT_NONALIASING. The cpu_architecture() function
returns the version of the supported MMU features (e.g. TEX remapping)
but it doesn't make any assumptions about the cache type. The patch adds
the checking of the Cache Type Register for the ARMv7 format.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
The target of the strex instruction to clear the exlusive monitor
is currently the top of the stack. If the store succeeeds this
corrupts r0 in pt_regs. Use the next stack location instead of
the current one to prevent any chance of corrupting an in-use
address.Signed-off-by: Seth Forshee
Signed-off-by: Russell King -
The following patch enables SMC911x support to work on the OMAP LDP
board. Although the SMC911x driver will eventually be obsoleted, the
smsc911x patches are rather invasive for the -rc kernels.Rather than risk destablising smsc911x, this simpler patch is preferred
to allow the network interface to work.Signed-off-by: Russell King
Acked-by: Tony Lindgren
Signed-off-by: David S. Miller
28 Feb, 2009
1 commit
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Now that the musb build fixes for DaVinci got merged (RC3?), kick in
the other bits needed to get it finally *working* in mainline:- Use clk_enable()/clk_disable() ... the "always enable USB clocks"
code this originally relied on has since been removed.- Initialize the USB device only after the relevant I2C GPIOs are
available, so the host side can properly enable VBUS.- Tweak init sequencing to cope with mainline's relatively late init
of the I2C system bus for power switches, transceivers, and so on.Sanity tested on DM6664 EVM for host and peripheral modes; that system
won't boot with CONFIG_PM enabled, so OTG can't yet be tested. Also
verified on OMAP3.(Unrelated: correct the MODULE_PARM_DESC spelling of musb_debug.)
Signed-off-by: David Brownell
Cc: Felipe Balbi
Signed-off-by: Greg Kroah-Hartman
25 Feb, 2009
2 commits
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Currently the unmask function for EINT interrupts was setting the mask
bit rather than clearing it. This was also previously reported and
fixed by Kyungmin Park and others.Acked-By: Ben Dooks
Signed-off-by: Mark Brown
Signed-off-by: Russell King -
Add the necessary i2c_board_info structure to fix the lack of PCF8583
RTC on RiscPC.Signed-off-by: Russell King
Signed-off-by: Jean Delvare
Cc: Alessandro Zummo
23 Feb, 2009
1 commit
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We've discovered that our AT91SAM9260 board consumed too much power when
returning from a slowclock low-power mode. RAM self-refresh is enabled in
a bootloader in our case, this is how we saw a difference. Estimated ca.
30mA more on 4V battery than the same state before powersaving.After a small research we found that there seems to be a bogus
sdram_selfrefresh_disable() call at the end of at91_pm_enter() call, which
overwrites the LPR register with uninitialized value. Please find the
suggested patch attached.This patch fixes correct restoring of LPR register of the Atmel AT91 SDRAM
controller when returning from a power saving mode.Signed-off-by: Andrei Birjukov
Acked-by: Andrew Victor
Signed-off-by: Andrew Morton
Signed-off-by: Russell King
20 Feb, 2009
1 commit
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Remove the gesbc9312.h header since it is unused.
Signed-off-by: H Hartley Sweeten
Signed-off-by: Russell King
19 Feb, 2009
3 commits
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READ_IMPLIES_EXEC must be set when:
o binary _is_ an executable stack (i.e. not EXSTACK_DISABLE_X)
o processor architecture is _under_ ARMv6 (XN bit is supported from ARMv6)Signed-off-by: Makito SHIOKAWA
Signed-off-by: Russell King -
When changing the parent of a clock, it is necessary to keep the
clock use counts balanced otherwise things the parent state will
get corrupted. Since we already disable and re-enable the clock,
we might as well use the recursive versions instead.Signed-off-by: Russell King
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In the non highmem case, if two memory banks of 1GB each are provided,
the second bank would evade suppression since its virtual base would
be 0. Fix this by disallowing any memory bank which virtual base
address is found to be lower than PAGE_OFFSET.Reported-by: Lennert Buytenhek
Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King
18 Feb, 2009
1 commit
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The GPIO interrupts can be configured as either level triggered or edge
triggered, with a default of level triggered. When an edge triggered
interrupt is requested, the gpio_irq_set_type method is called which
currently switches the given IRQ descriptor between two struct irq_chip
instances: orion_gpio_irq_level_chip and orion_gpio_irq_edge_chip. This
happens via __setup_irq() which also calls irq_chip_set_defaults() to
assign default methods to uninitialized ones. The problem is that
irq_chip_set_defaults() is called before the irq_chip reference is
switched, leaving the new irq_chip (orion_gpio_irq_edge_chip in this
case) with uninitialized methods such as chip->startup() causing a kernel
oops.Many solutions are possible, such as making irq_chip_set_defaults() global
and calling it from gpio_irq_set_type(), or calling __irq_set_trigger()
before irq_chip_set_defaults() in __setup_irq(). But those require
modifications to the generic IRQ code which might have adverse effect on
other architectures, and that would still be a fragile arrangement.
Manually copying the missing methods from within gpio_irq_set_type()
would be really ugly and it would break again the day new methods with
automatic defaults are added.A better solution is to have a single irq_chip instance which can deal
with both edge and level triggered interrupts. It is also a good idea
to switch the IRQ handler instead, as the edge IRQ handler allows for
one edge IRQ event to be queued as the IRQ is actually masked only when
that second IRQ is received, at which point the hardware can queue an
additional IRQ event, making edge triggered interrupts a bit more
reliable.Tested-by: Martin Michlmayr
Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King
17 Feb, 2009
1 commit
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Add support for inverted rdy_busy pin for Atmel nand device controller
It will fix building error on NeoCore926 board.Acked-by: Andrew Victor
Acked-by: David Woodhouse
Signed-off-by: Gregory CLEMENT
Signed-off-by: Russell King
15 Feb, 2009
2 commits
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Enable the GPIO clocks earlier in the initialization sequence. This
allow the board-setup code to read and set GPIO pins.Signed-off-by: Marc Pignat
Signed-off-by: Andrew Victor
Signed-off-by: Russell King -
The recently merged AT91SAM9 watchdog driver uses the
AT91SAM9X_WATCHDOG config variable, whereas the original version of
the driver (and the platform support code) used AT91SAM9_WATCHDOG.
This causes the watchdog platform_device to never be registered, and
therefore the driver not to be initialized.This patch:
- updates the platform support code to use AT91SAM9X_WATCHDOG.
- includes to fix compile error (same fix as was applied
to at91rm9200_wdt.c)
- fixes comment regarding watchdog clock-rates in at91rm9200.Signed-off-by: Andrew Victor
Signed-off-by: Russell King
14 Feb, 2009
2 commits
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_omap2_clksel_get_src_field() was returning the first entry which was
either the default _or_ applicable to the SoC. This is wrong - we
should be returning the first default which is applicable to the SoC.Signed-off-by: Russell King
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The error checks for omap2_divisor_to_clksel() and comment disagree with
the actual value returned on error. Fix this to return the correct error
value.Signed-off-by: Russell King
10 Feb, 2009
1 commit
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The C99 specification states in section 6.11.5:
The placement of a storage-class specifier other than at the beginning of the
declaration specifiers in a declaration is an obsolescent feature.Signed-off-by: Tobias Klauser
Signed-off-by: Russell King
09 Feb, 2009
1 commit
04 Feb, 2009
1 commit
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* master.kernel.org:/home/rmk/linux-2.6-arm:
NVRAM depends on RTC_DRV_CMOS
rename platform_driver name "flash" to "sa1100-mtd"
annotate that [fp, #-4] is the saved lr
Use __SPIN_LOCK_UNLOCKED to initialize bad_irq_desc.lock
ARM: OMAP: fix fault in enter_full_retention()
ARM: OMAP: Mask interrupts when disabling interrupts, v2
ARM: OMAP: gptimer min_delta_ns corrected
ARM: OMAP: Fix hsmmc init, v2
ARM: OMAP: Fix omap34xx revision detection for ES3.1
ARM: OMAP: DMA: Fix uninitialized channel flags
ARM: OMAP: Fix race in OMAP2/3 DMA IRQ handling
ARM: OMAP: Fix McBSP spin_lock deadlock
[ARM] 5366/1: fix shared memory coherency with VIVT L1 + L2 caches
[ARM] call undefined instruction exception handler with irqs enabled
[ARM] msm: fix build errors
[ARM] etherh: continue fixing build failure
03 Feb, 2009
1 commit
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This patch adds a MX2/MX3 specific SDHC driver. The hardware is basically
the same as in the MX1, but unlike the MX1 controller the MX2
controller just works as expected. Since the MX1 driver has more
workarounds for bugs than anything else I had no success with supporting
MX1 and MX2 in a sane way in one driver.Signed-off-by: Sascha Hauer
Signed-off-by: Pierre Ossman
02 Feb, 2009
1 commit
31 Jan, 2009
3 commits
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"flash" is a very generic name for a platform_driver that is only
available on SA11x0.Signed-off-by: Uwe Kleine-König
Cc: Nicolas Pitre -
Signed-off-by: Uwe Kleine-König
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SPIN_LOCK_UNLOCKED is deprecated as lockdep cannot properly work with
locks initialized with it.This fix is necessary to compile the linux-rt tree for ARM.
Signed-off-by: Uwe Kleine-König
Cc: Steven Rostedt
30 Jan, 2009
8 commits
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In omap24xx_cpu_suspend assembly routine, the r2 register which holds
the address of the SDRC_POWER reg is set to zero before the value is
written back triggering a fault due to writing to address zero.It's hard to tell where this change was introduced since this file
has been moved and merged.While this fix prevents a crash, suspend on my n810 is broken with
current kernels. I never come out of suspend.Signed-off-by: Kevin Hilman
Signed-off-by: Tony Lindgren -
By Ingo Molnar, interrupts are not masked by default.
(refer to 76d2160147f43f982dfe881404cfde9fd0a9da21)But if interrupts are not masked, the processor can wake up while in
Suspend-to-RAM state by an external interrupt. For example, if an
OMAP3 board is connected to Host PC by USB and entered to Suspend-to-RAM
state, it wake up automatically by M_IRQ_92. The disable_irq() function
can't disable the interrupt in H/W level, So I modified
arch/arm/mach-omap2/irq.cSigned-off-by: Kim Kyuwon
Signed-off-by: Tony Lindgren -
When 32 kHz timer is used the min_delta_ns should be initialized so
that it reflects the timer programming cost. A write to the timer
device will be usually posted, but it takes roughly 3 cycles before
it is effective. If the timer is reprogrammed before that, the CPU
will stall until the previous write completes. This was pointed out by
Richard Woodruff.Since the lower bound for min_delta_ns is 1000, the change is visible
only with tick rates less than 3 MHz.Also note that the old value is incorrect for 32 kHz also due to
a rounding error, and it can cause the timer queue to hang (due to
clockevent code trying to program the timer with zero ticks).Signed-off-by: Aaro Koskinen
Reviewed-by: Richard Woodruff
Signed-off-by: Tony Lindgren -
The naming accidentally broke while changing the name for the
driver to not to conflict with the other mmc driver.Signed-off-by: Tony Lindgren
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Fix omap34xx revision detection for ES3.1
Signed-off-by: Tony Lindgren
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This has similar symptoms than 66c23551b1b774e2be3c7bdf91c0ebf2c7a3519e
where just omap_request_dma, omap_dma_link_lch and omap_dma_unlink_lch
can cause incorrect dump_stack(). Here it can happen if channel has been
used before and the channel flags variable holds old status.Signed-off-by: Jarkko Nikula
Signed-off-by: Tony Lindgren -
CSR must be cleared before invoking the callback.
If the callback function starts a new, fast DMA transfer on the same
channel, the completion status might lost if CSR is cleared after
the callback invocation.Signed-off-by: Juha Yrjola
Signed-off-by: Tony Lindgren -
A spin_lock deadlock will occur when omap_mcbsp_request() is invoked.
omap_mcbsp_request()
\- clk_enable(mcbsp->clk) [takes and holds clockfw_lock]
\- omap2_clk_enable()
\- _omap2_clk_enable()
\- omap_mcbsp_clk_enable()
\- clk_enable(child clock) [tries for clockfw_lock again]mcbsp_clk is a virtual clock and it comprises several child clocks. when
enable mcbsp_clk in omap_mcbsp_request(), the enable function of mcbsp_clk
will enable its child clocks, then the deadlock occurs.The solution is to remove the virtual clock and enable these child clocks in
omap_mcbsp_request() directly.Signed-off-by: Stanley.Miao
Signed-off-by: Tony Lindgren
29 Jan, 2009
1 commit
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When there are multiple L1-aliasing userland mappings of the same physical
page, we currently remap each of them uncached, to prevent VIVT cache
aliasing issues. (E.g. writes to one of the mappings not being immediately
visible via another mapping.) However, when we do this remapping, there
could still be stale data in the L2 cache, and an uncached mapping might
bypass L2 and go straight to RAM. This would cause reads from such
mappings to see old data (until the dirty L2 line is eventually evicted.)This issue is solved by forcing a L2 cache flush whenever the shared page
is made L1 uncacheable.Ideally, we would make L1 uncacheable and L2 cacheable as L2 is PIPT. But
Feroceon does not support that combination, and the TEX=5 C=0 B=0 encoding
for XSc3 doesn't appear to work in practice.Signed-off-by: Nicolas Pitre
Signed-off-by: Russell King
28 Jan, 2009
1 commit
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Aaro says:
> With spinlock debugs enabled I get might_sleep() warnings when using
> ptrace.tracked down to a missing enable_irq before calling do_undefinstr().
Reported-by: Aaro Koskinen
Tested-by: Aaro Koskinen
Signed-off-by: Russell King