09 Jun, 2017

2 commits

  • WM8960 derives bit clock from sysclock using BCLKDIV[3:0] of R8
    clocking register (See WM8960 datasheet, page 71).

    There are use cases, like this:
    aplay -Dhw:0,0 -r 48000 -c 1 -f S20_3LE -t raw audio48k20b_3LE1c.pcm

    where no BCLKDIV applied to sysclock can give us the exact requested
    bitclk, so driver fails to configure clocking and aplay fails to run.

    Fix this by relaxing bitclk computation, so that when no exact value
    can be derived from sysclk pick the closest value greater than
    expected bitclk.

    Suggested-by: Charles Keepax
    Signed-off-by: Daniel Baluta

    Daniel Baluta
     
  • Add a separate function for finding (sysclk, lrclk, bclk)
    when the clock is auto or mclk. This makes code easier to
    read and reduces the indentation level in wm8960_configure_clocking.

    Signed-off-by: Daniel Baluta
    Acked-by: Charles Keepax

    Daniel Baluta
     

08 Jun, 2017

23 commits


23 Feb, 2017

15 commits