12 Feb, 2019
40 commits
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Move iMX8 HDP CEC driver to MXC folder.
Signed-off-by: Sandor Yu
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enable imx8mm pcie support.
BTW, the power management is not supported yet.
Disable pcie module, if you test power management
on the imx8mm platforms.Signed-off-by: Richard Zhu
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Set the parent clks of pcie.
Signed-off-by: Richard Zhu
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Change the pcie phy region in dts accordingly.
Signed-off-by: Richard Zhu
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Add the pcie support for imx8mm and verify
it on imx8mm evk board when internal pll is
used as ref clock.Signed-off-by: Richard Zhu
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Replace "snd_soc_read" calls with "ak4497_read" calls in order
to log the read errors. Aside of this use "gpio_is_valid" call
to validate the gpio values and "gpio_set_value_cansleep" call
in order to signal the "can sleep" context.Signed-off-by: Shengjiu Wang
Signed-off-by: Viorel Suman -
and Linux calling
Change g_fmt and s_fmt to make it compitable with Andriod and Linux
calling for vpu decoderSigned-off-by: Huang Chaofan
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Signed-off-by: GuoRui
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Fix eos hang issue for vpu decoder on mek B0 board
Signed-off-by: Huang Chaofan
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perf stat -a -e ddr0/axid-read,axi_id=MMMMDDDD/ cmd
MMMM AXI_MASKING
DDDD AXI_IDSigned-off-by: Frank Li
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Enable DDR monitor
Signed-off-by: Frank Li
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Add iMX8MM PDM pins header.
Signed-off-by: Cosmin-Gabriel Samoila
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The vendor tree does imx7 PGC management through regulator notifiers
while upstream implemented the same features using power domains. These
two drivers have entirely different interfaces with higher-level IP
blocks.Resolve this conflict by moving the old code to drivers/soc and
supporting both power-domain and regulator interfaces. This effectively
merges the two drivers and is similar to how imx6sx implements both
power domains and a regulator notifier for pcie specifically.Supporting both interfaces allows consumes to switch one-by-one, for
example by having PCI work with a power-domains reference while usb hsic
still uses the regulator enable/disable interface.Signed-off-by: Leonard Crestez
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The power domain code shares the same node and will not probe if irqchip
probes first and marks the node with OF_POPULATED.Clearing the OF_POPULATED flag is also done in imx_gpc_init for imx6 and
imx_gpcv2_irqchip_init implemented by upstream.In imx_4.9.y this was solved in a different way by adding a second pgc
node, see commit fab513930e78 ("MLK-14280: gpc: gpc driver not probed").
Solving the problem by clearing OF_POPULATED allows using the upstream
PGC driver without hacks.Having two irqchip implementations with same name seems to work fine
with the mach-imx variant taking precedence.Signed-off-by: Leonard Crestez
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Correct MIPI/PCIe/USB_HSIC's PGC offset based on
design RTL, the value on Reference Manual are incorrect.The correct offset should be as below:
0x800 ~ 0x83F: PGC for core0 of A7 platform;
0x840 ~ 0x87F: PGC for core1 of A7 platform;
0x880 ~ 0x8BF: PGC for SCU of A7 platform;
0xA00 ~ 0xA3F: PGC for fastmix/megamix;
0xC00 ~ 0xC3F: PGC for MIPI PHY;
0xC40 ~ 0xC7F: PGC for PCIe_PHY;
0xC80 ~ 0xCBF: PGC for USB OTG1 PHY;
0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY;
0xD00 ~ 0xD3F: PGC for USB HSIC PHY;Signed-off-by: Anson Huang
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Add micfil DAI node in dtsi and pdm sound card in dts.
We also moved ak5558 nodes into separate dts since
ak5558 uses sai5 which share some pins with micfil.Signed-off-by: Cosmin-Gabriel Samoila
(cherry picked from commit 8451c6886b0175b7e1391293aa9fb461395f8485) -
Register offset needs to be applied on mapbase also.
dma_tx/rx_request use the physical address of UARTDATA.
Register offset is currently only applied to membase (the
corresponding virtual addr) but not on mapbase.Reviewed-by: Leonard Crestez
Acked-by: Fugang Duan
Signed-off-by: Adriana Reus -
- mu is used by rpmsg on imx8mm, add the mu root clk.
- check the m4 is enable or not.Signed-off-by: Richard Zhu
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enable rpmsg on imx8mm
Signed-off-by: Richard Zhu
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Enable AK4497 with mode 0. For ak4497 the same SAI interface as
for AK4458 is used, so a separate ak4497 dts is needed.Signed-off-by: Shengjiu Wang
Signed-off-by: Viorel Suman -
When enabling the panel, the initial brightness level was hard-coded to
0x20. This way, during a suspend/resume cycle, after resume, this
hard-coded brightness was used, instead of the one before suspend.
Removing the hard-coded level and using the one stored in backlight
device.Signed-off-by: Robert Chiras
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Added no_clk_reset property for 8M dts files, since DSI doesn't need
it's clocks stopped during suspend.
Also, added power on delay for 8QM and 8QXP for a better suspend/resume
stability.Signed-off-by: Robert Chiras
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On some platforms, like the i.MX8M, the Display Controller is not
completely powered off during suspend, just stopped. Since there are
problems if we stop the clocks in DSI sub-system, while the Display
Controller is still powered on, the display clocks will get out of sync.
Adding this new property to specify, on such platforms, not to reset the
clocks.Signed-off-by: Robert Chiras
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Remove the NO_CLK_RESET define and add a property for this.
On some platforms, like the i.MX8M, the Display Controller is not
completely powered off during suspend, just stopped. Since there are
problems if we stop the clocks in DSI sub-system, while the Display
Controller is still powered on, the display clocks will get out of sync.
Adding this new property to specify, on such platforms, not to reset the
clocks.Signed-off-by: Robert Chiras
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Signed-off-by: Antoine Bouyer
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These pointers are required for drm dts
Signed-off-by: Antoine Bouyer
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[Patch] Pulling the following commits and some general changes
from custom v3.10 kernel for supporting qcacld2.0 on kernel v4.9.11.
1. cfg80211: Using new wiphy flag WIPHY_FLAG_DFS_OFFLOAD
When flag WIPHY_FLAG_DFS_OFFLOAD is defined, the driver would handle
all the DFS related operations. Therefore the kernel needs to ignore
the DFS state that it uses to block the userspace calls to the driver
through cfg80211 APIs. Also it should treat the userspace calls to
start radar detection as a no-op.Please note that changes in util.c is not picked up explicitly.
Kernel v4.9.11 uses wrapper cfg80211_get_chans_dfs_required which takes
care of this change.Change-Id: I9dd2076945581ca67e54dfc96dd3dbc526c6f0a2
IRs-Fixed: 2026862. New db.txt from git/sforshee/wireless-regdb.git
CONFIG_CFG80211_INTERNAL_REGDB is enabled in build. This causes
kernel warn messages as db.txt is empty. A new db.txt is added
from:
git://git.kernel.org/pub/scm/linux/kernel/git/sforshee/wireless-regdb.gitIRs-Fixed: 202686
3. Picked up the declaration and definition of the function
cfg80211_is_gratuitous_arp_unsolicited_naChange-Id: I1e4083a2327c121073226aa6b75bb6b5b97cec00
CRs-fixed: 1079453Signed-off-by: Nakul Kachhwaha
Signed-off-by: Fugang Duan -
Allow the CONFIG_SPI_IMX option to be built by default.
Signed-off-by: Fabio Estevam
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The spi_imx IP block is also present on i.MX8M, so allow it
to be built for this platform.Signed-off-by: Fabio Estevam
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Add support for the three ECSPI ports present on i.MX8MQ.
Signed-off-by: Fabio Estevam
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multi-instance for vpu decoder
Create multi workqueue for different instance to run multi-instance for
vpu decoder, in case that when one instance hang, it will impact othersSigned-off-by: Huang Chaofan
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Fix reboot failure on i.mx845s evk board. For BD71837, BUCKx_SEL and
BUCKx_EN of all bucks can't be set to 1 as explicity enabled or disabled,
otherwise, it may mess up with the default state machine if pmic reset
triggered. Remove enable/disable interfaces in driver to avoid touch such
bits.Signed-off-by: Robin Gong
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As blit engine use cmd sequence and disabled hardware interrupt,
sync to wait the cmd sequence idle before execute new cmd sequenceSigned-off-by: Yuchou Gan
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As to super-tiled format for blit engine, the dprc
width should aligned to smaller size instead of 64.Signed-off-by: Yuchou Gan
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Blit engine need arbitrary crop, but ULC can only lie on block boundary,
prg stride should be bigger than (width + align_margin) * bpp / 8Signed-off-by: Yuchou Gan
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h1 encoder code refine
Signed-off-by: Zhou Peng
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These are similar to their counterpart non-A0 dtbs, but vpu encoder
and decoder are removed.Signed-off-by: Adriana Reus
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In order to enlarge the CMA easily, change the rpmsg
reserved memory region from 0xb800_0000 to 0x9000_0000.
And refine the layout of the reserved memory.
- RPMSG buffers are allocated from CMA dynamically, and have to
be accessed by M4 side. But M4 can only access the 1.5Gbytes
DDR memory from 0x8000_0000. So, the finial reserved memory
layout is just like the one below.Thus, the largest size of the DDR memory left for CMA, is about
1212Mbytes in theory, since 32Mbytes alignment is required by
CMA allocation.reserved-memory layout
0x8800_0000 ~ 0x8FFF_FFFF M4 + RTOS(128M)
0x9000_0000 ~ 0x903F_FFFF RPMSG Vring(4M)
0x9440_0000 ~ 0xDFFF_FFFF(MAX) CMA(1212M)(MAX)Signed-off-by: Richard Zhu
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Update cpufreq set-points according to SCFW changes:
A53: add 1104MHz setpoint;
A72: add 1300MHz setpoint.Signed-off-by: Anson Huang
Reviewed-by: Robin Gong -
g2d_buf_from_fd use gcoHAL_WrapUserMemory to wrap dmabuf handle,
and then use gcoOS_LockVideoMemory to retrieve physical address.dmabuf is contiguous, need set contiguous flag to avoid MMU mapping,
otherwise g2d_buf_from_fd return the invalid physical address,Signed-off-by: Xianzhong