12 Oct, 2011
1 commit
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Add:
- Setup dts node for USB
- pin description and setup for SMC1 (serial interface)Update and cleanup mgcoge_defconfig:
- enable: TIPC, UBIFS, USB_GADGET driver, SQUASHFS, HIGHRES timers
POSIX_MQUEUE, EMBEDDED
- disable: EXT3, PPC_PMACSigned-off-by: Holger Brunck
Acked-by: Heiko Schocher
cc: Kumar Gala
Signed-off-by: Kumar Gala
07 Oct, 2011
10 commits
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If the L1 D-Cache is in write shadow mode the HW will auto-recover the
error. However we might still log the error and cause a machine check
(if L1CSR0[CPE] - Cache error checking enable). We should only treat
the non-write shadow case as non-recoverable.Signed-off-by: Kumar Gala
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We already have cpu a005 errata handler when instruction cannot be
recognized. Before we lookup the inst, there's type checking, and we also
need to handle it in errata handler when the type checking failed.Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala -
Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala -
Signed-off-by: Liu Yu
Signed-off-by: Kumar Gala -
There's only p2041rdb board for official release, but the p2041 silicon
on the board can be converted to p2040 silicon without XAUI and L2 cache
function, then the board becomes p2040rdb board. so we use the file name
p2041_rdb.c to handle P2040RDB board and P2041RDB board which is also
consistent with the board name under U-Boot.During the rename we make few other minor changes to the device tree:
* Move USB phy setting into p2041si.dtsi as its SoC not board defined
* Convert PCI clock-frequency to decimal to be more readableSigned-off-by: Mingkai Hu
Signed-off-by: Kumar Gala -
The P4080 silicon device tree was using PowerPC,4080 while the other
e500mc based SoCs used PowerPC,e500mc. Use the core name to be
consistent going forward.Signed-off-by: Kumar Gala
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Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
If CONFIG_PHYS_ADDR_T_64BIT is set, compilation of sbc8560 fails with
the following error:arch/powerpc/platforms/85xx/sbc8560.c: In function ‘sbc8560_bdrstcr_init’:
arch/powerpc/platforms/85xx/sbc8560.c:286: error: format ‘%x’ expects type ‘unsigned int’, but argument 2 has type ‘resource_size_t’Fix that by using %pR format instead of just printing the start of
resource.Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala
29 Sep, 2011
4 commits
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The firmware on old 970 blades supports some kind of takeover called
"TNK takeover" which will crash if we try to probe for OPAL takeover,
so don't do it.Signed-off-by: Benjamin Herrenschmidt
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The current L1 cache read event code 0x80082 only counts for thread 0. The
event code 0x280030 should be used to count events on thread 0 and 1. The
patch fixes the event code for the L1 cache read.The current L1 cache write event code 0x80086 only counts for thread 0. The
event code 0x180032 should be used to count events on thread 0 and 1. The
patch fixes the event code for the L1 cache write.FYI, the documentation lists three event codes for the L1 cache read event
and three event codes for the L1 cache write event. The event description
for the event codes is as follows:L1 cache read requests 0x80082 LSU 0 only
L1 cache read requests 0x8008A LSU 1 only
L1 cache read requests 0x80030 LSU 1 or LSU 0, counter 2 only.L1 cache store requests 0x80086 LSU 0 only
L1 cache store requests 0x8008E LSU 1 only
L1 cache store requests 0x80032 LSU 0 or LSU 1, counter 1 only.There can only be one request from either LSU 0 or 1 active at a time.
Signed-off-by: Carl Love
Acked-by: Paul Mackerras
Signed-off-by: Benjamin Herrenschmidt -
gcc (rightfully) complains that we are accessing beyond the
end of the fpr array (we do, to access the fpscr).The only sane thing to do (whether anything in that code can be
called remotely sane is debatable) is to special case fpscr and
handle it as a separate statement.I initially tried to do it it by making the array access conditional
to index < PT_FPSCR and using a 3rd else leg but for some reason gcc
was unable to understand it and still spewed the warning.So I ended up with something a tad more intricated but it seems to
build on 32-bit and on 64-bit with and without VSX.Signed-off-by: Benjamin Herrenschmidt
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Based on patch by David Gibson
xmon has a longstanding bug on systems which are SMP-capable but lack
the MSR[RI] bit. In these cases, xmon invoked by IPI on secondary
CPUs will not properly keep quiet, but will print stuff, thereby
garbling the primary xmon's output. This patch fixes it, by ignoring
the RI bit if the processor does not support it.There's already a version of this for 4xx upstream, which we'll need
to extend to other RI-lacking CPUs at some point. For now this adds
Book3e processors to the mix.Signed-off-by: Jimi Xenidis
Signed-off-by: Benjamin Herrenschmidt
26 Sep, 2011
1 commit
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We don't want to configure PCI Express Max Payload Size or
Max Read Request Size on systems that set that flag. The
firmware will have done it for us, and under hypervisors such
as pHyp we don't even see the parent switches and bridges and
thus can make no assumption on what values are safe to use.Signed-off-by: Benjamin Herrenschmidt
23 Sep, 2011
9 commits
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Some devices have a dma-window that starts at the address 0. This allows
DMA addresses to be mapped to this address and returned to drivers as a
valid DMA address. Some drivers may not behave well in this case, since
the address 0 is considered an error or not allocated.The solution to avoid this kind of error from happening is reserve the
page addressed as 0 so it cannot be allocated for a DMA mapping.Signed-off-by: Thadeu Lima de Souza Cascardo
Signed-off-by: Benjamin Herrenschmidt -
Commit 41151e77a4 ("powerpc: Hugetlb for BookE") added some
#ifdef CONFIG_MM_SLICES conditionals to hugetlb_get_unmapped_area()
and vma_mmu_pagesize(). Unfortunately this is not the correct config
symbol; it should be CONFIG_PPC_MM_SLICES. The result is that
attempting to use hugetlbfs on 64-bit Power server processors results
in an infinite stack recursion between get_unmapped_area() and
hugetlb_get_unmapped_area().This fixes it by changing the #ifdef to use CONFIG_PPC_MM_SLICES
in those functions and also in book3e_hugetlb_preload().Signed-off-by: Paul Mackerras
Signed-off-by: Benjamin Herrenschmidt -
Activate all MPC512x related boards. Also enable GPIO-driver, SPI driver
and at25 to test SPI. Enable DEVTMPFS. Bump to 3.1-rc6.Signed-off-by: Wolfram Sang
Cc: Anatolij Gustschin
Cc: Benjamin Herrenschmidt
Signed-off-by: Anatolij Gustschin -
Move the driver to the place where it is expected to be nowadays. Also
rename its CONFIG-name to match the rest and adapt the defconfigs.
Finally, move selection of REQUIRE_GPIOLIB or WANTS_OPTIONAL_GPIOLIB to
the platforms, because this option is per-platform and not per-driver.Signed-off-by: Wolfram Sang
Cc: Anatolij Gustschin
Cc: Grant Likely
Cc: Benjamin Herrenschmidt
Acked-by: Grant Likely
Signed-off-by: Anatolij Gustschin -
Audio support for the MPC5200 exists, so enable it by default.
Signed-off-by: Timur Tabi
Acked-by: Wolfram Sang
Signed-off-by: Anatolij Gustschin -
We use both MSCAN controllers on this board, so do not disable
them in the device tree.Signed-off-by: Anatolij Gustschin
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timer0 and timer1 pins are used as simple GPIO on this board.
Add gpio-controller and #gpio-cells properties to timer nodes
so that we can control gpio lines using available MPC52xx
GPT driver.Signed-off-by: Anatolij Gustschin
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Add new nodes to describe more hardware the board is
equipped with:
- two can nodes for SJA1000 on localbus
- pci node to support Coral-PA graphics controller
- serial node for SC28L92 DUART on localbus
- spi node for MSP430 deviceAlso correct i2c eeprom node name.
Signed-off-by: Heiko Schocher
Signed-off-by: Anatolij Gustschin -
Both, #address-cells and #size-cells properties are required
for spi bus node, so add them.Signed-off-by: Anatolij Gustschin
20 Sep, 2011
15 commits
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perf events, powerpc: Add POWER7 stalled-cycles-frontend/backend events
Extent the POWER7 PMU driver with definitions for generic front-end and back-end
stall events.As explained in Ingo's original comment(8f62242246351b5a4bc0c1f00c0c7003edea128a
), the exact definitions of the stall events are very much processor specific asdifferent things mean different in their respective instruction pipeline. These
two Power7 raw events are the closest approximation to the concept detailed in
Ingo's comment.[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */
It means cycles when the Global Completion Table has no slots from this thread[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */
It means no groups completed and GCT not empty for this threadSigned-off-by: Anshuman Khandual
Signed-off-by: Benjamin Herrenschmidt -
The firmware doesn't wait after lifting the PCI reset. However it does
timestamp it in the device tree. We use that to ensure we wait long
enough (3s is our current arbitrary setting) from that timestamp to
actually probing the bus.Signed-off-by: Benjamin Herrenschmidt
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This implements support for MSIs on p5ioc2 PHBs. We only support
MSIs on the PCIe PHBs, not the PCI-X ones as the later hasn't been
properly verified in HW.Signed-off-by: Benjamin Herrenschmidt
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This adds support for PCI-X and PCIe on the p5ioc2 IO hub using
OPAL. This includes allocating & setting up TCE tables and config
space access routines.This also supports fallbacks via RTAS when OPAL is absent, using
legacy TCE format pre-allocated via the device-tree (BML style)Signed-off-by: Benjamin Herrenschmidt
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OPAL can handle various interrupt for us such as Machine Checks (it
performs all sorts of recovery tasks and passes back control to us with
informations about the error), Hardware Management Interrupts and Softpatch
interrupts.This wires up the mechanisms and prints out specific informations returned
by HAL when a machine check occurs.Signed-off-by: Benjamin Herrenschmidt
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We do the minimum which is to "pass" interrupts to HAL, which
makes the console smoother and will allow us to implement
interrupt based completion and console.Signed-off-by: Benjamin Herrenschmidt
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OPAL handles HW access to the various ICS or equivalent chips
for us (with the exception of p5ioc2 based HEA which uses adifferent backend) similarily to what RTAS does on pSeries.
Signed-off-by: Benjamin Herrenschmidt
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Implements OPAL RTC and NVRAM support and wire all that up to
the powernv platform.We use RTAS for RTC as a fallback if available. Using RTAS for nvram
is not supported yet, pending some rework/cleanup and generalization
of the pSeries & CHRP code. We also use RTAS fallbacks for power off
and rebootSigned-off-by: Benjamin Herrenschmidt
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This calls the respective HAL functions, and spin on hal_poll_event()
to ensure the HAL has a chance to communicate with the FSP to trigger
the reboot or shutdown operationSigned-off-by: Benjamin Herrenschmidt
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This adds a udbg and an hvc console backend for supporting a console
using the OPAL console interfaces.On OPAL v1 we have hvc0 mapped to whatever console the system was
configured for (network or hvsi serial port) via the service
processor.On OPAL v2 we have hvcN mapped to the Nth console provided by OPAL
which generally corresponds to:hvc0 : network console (raw protocol)
hvc1 : serial port S1 (hvsi)
hvc2 : serial port S2 (hvsi)Note: At this point, early debug console only works with OPAL v1
and shouldn't be enabled in a normal kernel.Signed-off-by: Benjamin Herrenschmidt
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OPAL v2 is instantiated in a way similar to RTAS using Open Firmware
client interface calls, and the resulting address and entry point are
put in the device-treeSigned-off-by: Benjamin Herrenschmidt
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Add definition of OPAL interfaces along with the wrappers to call
into OPAL runtime and the early device-tree parsing hook to locate
the OPAL runtime firmware.Signed-off-by: Benjamin Herrenschmidt
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We stash it in boot_command_line which isn't in BSS and so won't
be overwritten. We then use that as a default cmd_line before
we walk the device-tree.Signed-off-by: Benjamin Herrenschmidt
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On machines supporting the OPAL firmware version 1, the system
is initially booted under pHyp. We then use a special hypercall
to verify if OPAL is available and if it is, we then trigger
a "takeover" which disables pHyp and loads the OPAL runtime
firmware, giving control to the kernel in hypervisor mode.This patch add the necessary code to detect that the OPAL takeover
capability is present when running under PowerVM (aka pHyp) and
perform said takeover to get hypervisor control of the processor.To perform the takeover, we must first use RTAS (within Open
Firmware runtime environment) to start all processors & threads,
in order to give control to OPAL on all of them. We then call
the takeover hypercall on everybody, OPAL will re-enter the kernel
main entry point passing it a flat device-tree.Signed-off-by: Benjamin Herrenschmidt
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Unplugged CPU go into NAP mode in a loop until woken up
Signed-off-by: Benjamin Herrenschmidt
