07 May, 2015

2 commits


20 Mar, 2015

1 commit

  • System will be no response after resume back under low busfreq mode. The
    root cause of this issue is that when the system is under ultra_low_bus_freq
    mode on i.MX6SL, resume process has a low bus mode deamon in background,
    cause system enter low bus mode twice, busfreq driver will notify thermal
    driver to turn off PLL3 twice, and cause PLL3 usecount incorrect and UART
    no message out.

    Signed-off-by: Bai Ping

    Bai Ping
     

06 Mar, 2015

1 commit


05 Mar, 2015

1 commit

  • In imx6sl/sx dts, the lcdif display bpp is setting to 16,
    and sii902x hdmi driver bpp is 32.
    The sii902x driver will overwrite the display bpp when it loading,
    but some module such as v4l2 output driver is misses bpp change event.
    So align sii902x hdmi driver bpp with lcdif display bpp.

    Signed-off-by: Sandor Yu
    (cherry picked from commit 0fd274cc93a71c8636551c17d7d4157e97fe5cf2)

    Sandor Yu
     

04 Mar, 2015

2 commits


02 Mar, 2015

1 commit

  • Fix the clock index for cfg clock and use MACRO instead of hard-codes.

    This patch fixes the following issue.
    -----------------------------------------------------------
    root@imx6qdlsolo:~# /unit_tests/mxc_v4l2_capture.out -d /dev/video1 1.yuv
    in_width = 176, in_height = 144
    out_width = 176, out_height = 144
    top = 0, left = 0
    mipi csi2 can not receive sensor clk!
    ...

    ERROR: v4l2 capture: mxc_v4l_dqueue timeout enc_counter 0
    VIDIOC_DQBUF failed.ERROR: v4l2 capture: VIDIOC_QBUF: buffer already queued
    -----------------------------------------------------------

    Signed-off-by: Robby Cai
    (cherry picked from commit 6e4ee449de591d3cfb93575ca639ca32944832bc)

    Robby Cai
     

26 Feb, 2015

2 commits


12 Feb, 2015

2 commits


11 Feb, 2015

7 commits


09 Feb, 2015

2 commits

  • Add hwrng support for i.MX6SL.

    1. Add RNG driver. This driver originated as fsl-rngc.c. It
    has been modified to support device tree. The name has been
    changed since it supports both b and c variants of RNG.
    2. Added clock and compatible info to the device tree data.
    3. Added the entry in the options in the Kconfig for hwrng.

    (cherry picked from commit 1f3f2c0647b7319c4e23293a61512e4191593513)
    [: Edited to apply to 3.14]

    Signed-off-by: Dan Douglass
    Signed-off-by: Victoria Milhoan
    (cherry picked from commit 586166b87eee2e5ec40331032aed8c8eaec884f3)

    Dan Douglass
     
  • This patch is refined from the previous commit 20d89c9c909:

    -Update the parent of gpu2d_core for mx6dl.
    -Update the parent of gpu3d_shader and gpu3d_core for mx6dl.
    -Update the clock of gpu3d_shader and gpu3d_core for mx6dl.
    The code change is cherry-picked from patch 00e75bcba16d.

    Signed-off-by: Loren Huang
    Signed-off-by: Xianzhong
    Acked-by: Jason Liu
    (cherry picked from commit e63222bdba7c2de063c6367017ccd6a1d1d3cc22)

    Xianzhong
     

03 Feb, 2015

1 commit

  • LDO2p5 cannot be disabled in low power idle mode when the USB driver
    enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy
    regulator that the USB driver will enable when VBUS wakeup is required.

    This patch is copied from commit 7d849e4d9ebca3c as code the structure has
    changed too many. directly cherry-pick has too many conflicts to resolve

    Signed-off-by: Bai Ping

    Bai Ping
     

02 Feb, 2015

5 commits


01 Feb, 2015

1 commit


31 Jan, 2015

1 commit


30 Jan, 2015

6 commits


29 Jan, 2015

1 commit


28 Jan, 2015

4 commits

  • As spdif driver will register SPDIF clock to regmap, regmap will do
    clk_prepare in init function, so SPDIF clock is prepared in probe, then its
    root clock (pll clock) is prepared also, which cause the arm can't enter
    low power mode.
    Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
    Its root clock is ipg clock, and register it to regmap, then the issue can be
    fixed.

    Signed-off-by: Shengjiu Wang

    Shengjiu Wang
     
  • As spdif driver will register SPDIF clock to regmap, regmap will do
    clk_prepare in init function, so SPDIF clock is prepared in probe, then its
    root clock (pll clock) is prepared also, which cause the arm can't enter
    low power mode.
    Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
    Its root clock is ipg clock, and register it to regmap, then the issue can be
    fixed.

    Signed-off-by: Shengjiu Wang

    Shengjiu Wang
     
  • As spdif driver will register SPDIF clock to regmap, regmap will do
    clk_prepare in init function, so SPDIF clock is prepared in probe, then its
    root clock (pll clock) is prepared also, which cause the arm can't enter
    low power mode.
    Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
    Its root clock is ipg clock, and register it to regmap, then the issue can be
    fixed.

    Signed-off-by: Shengjiu Wang

    Shengjiu Wang
     
  • Enable various crypto algorithms in the default kernel configuration
    for i.MX6 devices.

    Signed-off-by: Victoria Milhoan

    Victoria Milhoan