27 Nov, 2011
1 commit
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The bitops functions (e.g. _test_and_set_bit) on ARM do not have unwind
annotations and therefore the kernel cannot backtrace out of them on a
fatal error (for example, NULL pointer dereference).This patch annotates the bitops assembly macros with UNWIND annotations
so that we can produce a meaningful backtrace on error. Callers of the
macros are modified to pass their function name as a macro parameter,
enforcing that the macros are used as standalone function implementations.Acked-by: Dave Martin
Signed-off-by: Will Deacon
Signed-off-by: Russell King
20 Feb, 2011
1 commit
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The kernel doesn't officially need to interwork, but using BX
wherever appropriate will help educate people into good assembler
coding habits.BX is appropriate here because this code is predicated on
__LINUX_ARM_ARCH__ >= 6Signed-off-by: Dave Martin
Acked-by: Nicolas Pitre
Signed-off-by: Russell King
03 Feb, 2011
2 commits
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Switch the set/clear/change bitops to use the word-based exclusive
operations, which are only present in a wider range of ARM architectures
than the byte-based exclusive operations.Tested record:
- Nicolas Pitre: ext3,rw,le
- Sourav Poddar: nfs,le
- Will Deacon: ext3,rw,le
- Tony Lindgren: ext3+nfs,leReviewed-by: Nicolas Pitre
Tested-by: Sourav Poddar
Tested-by: Will Deacon
Tested-by: Tony Lindgren
Signed-off-by: Russell King -
Add additional instructions to our assembly bitops functions to ensure
that they only operate on word-aligned pointers. This will be necessary
when we switch these operations to use the word-based exclusive
operations.Signed-off-by: Russell King
14 Aug, 2009
1 commit
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Before this patch enabling and disabling irqs in assembler code and by
the hardware wasn't tracked completly.I had to transpose two instructions in arch/arm/lib/bitops.h because
restore_irqs doesn't preserve the flags with CONFIG_TRACE_IRQFLAGS=ySigned-off-by: Uwe Kleine-König
Cc: Russell King
Cc: Peter Zijlstra
Cc: Ingo MolnarSigned-off-by: Uwe Kleine-König
29 May, 2009
1 commit
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Mathieu Desnoyers pointed out that the ARM barriers were lacking:
- cmpxchg, xchg and atomic add return need memory barriers on
architectures which can reorder the relative order in which memory
read/writes can be seen between CPUs, which seems to include recent
ARM architectures. Those barriers are currently missing on ARM.- test_and_xxx_bit were missing SMP barriers.
So put these barriers in. Provide separate atomic_add/atomic_sub
operations which do not require barriers.Reported-Reviewed-and-Acked-by: Mathieu Desnoyers
Signed-off-by: Russell King
21 May, 2007
1 commit
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Spelling fixes in arch/arm/.
Signed-off-by: Simon Arlott
Signed-off-by: Russell King
01 Jul, 2006
1 commit
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Signed-off-by: Jörn Engel
Signed-off-by: Adrian Bunk
09 Nov, 2005
1 commit
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save_and_disable_irqs does not need to use mov + msr (which was
introduced to work around a documentation bug which was propagated
into binutils.) Use msr with an immediate constant, and if we're
building for ARMv6 or later, use the new CPSID instruction.Signed-off-by: Russell King
03 Nov, 2005
1 commit
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The 'K' extension adds several new instructions to the ARMv6 ISA
which are primerily useful for SMP.Signed-off-by: Russell King
10 Aug, 2005
1 commit
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Signed-off-by: Russell King
29 Jul, 2005
1 commit
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We sometimes forgot to check whether the exclusive store succeeded.
Ensure that we always check. Also ensure that we always use the
out of line versions, since the inline versions are not SMP safe.Signed-off-by: Russell King
28 Jul, 2005
1 commit
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If we found that the bit was already in the desired state, we
would skip performing the operation, and write random data back.Signed-off-by: Russell King
16 Jul, 2005
1 commit
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Signed-off-by: Russell King
19 Apr, 2005
1 commit
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Signed-off-by: Russell King