27 Sep, 2010

1 commit

  • The PL310 on the ct-ca9x4 tile for the Versatile Express does not need
    to add additional latency when accessing its cache RAMs. Unfortunately,
    the boot monitor sets this up for an 8-cycle delay on reads and writes,
    resulting in greatly reduced memory performance when the L2 cache is
    enabled.

    This patch sets the L2 RAM latencies to the correct value of 1 cycle
    on the ct-ca9x4 tile before enabling the L2 cache.

    Acked-by: Catalin Marinas
    Signed-off-by: Will Deacon
    Signed-off-by: Russell King

    Will Deacon
     

25 Sep, 2010

10 commits


23 Sep, 2010

3 commits

  • When the policy for user space is to ignore misaligned accesses from user
    space, the processor then performs a documented rotation on the accessed
    data. This is the result of the access being trapped, and the kernel
    disabling the alignment trap before returning to user space again.

    In kernel space we always want misaligned accesses to be fixed up. This
    is enforced by always re-enabling the alignment trap on every entry into
    kernel space from user space. No such re-enabling is performed when an
    exception occurs while already in kernel space as the alignment trap is
    always supposed to be enabled in that case.

    There is however a small race window when a misaligned access in user
    space is trapped and the alignment trap disabled, but the CPU didn't
    return to user space just yet. Any exception would be entered from kernel
    space at that point and the kernel would then execute with the alignment
    trap disabled.

    Thanks to Maxime Bizon for providing a test module
    that made this issue reproducible.

    Signed-off-by: Nicolas Pitre
    Signed-off-by: Russell King

    Nicolas Pitre
     
  • Use a correct udelay value to get bus speed around 100KHz. The udelay
    value was most likely copied from the older devices, but the 9g45
    is signicantly faster (400MHz, DDR, ..), so a udelay of 2 gives a
    bus speed of around 190KHz, which is too fast for some devices.
    A udelay value of 5 gives a bus speed of around 90KHz here.

    Signed-off-by: Peter Korsgaard
    Signed-off-by: Nicolas Ferre
    Signed-off-by: Russell King

    Peter Korsgaard
     
  • Russell King
     

20 Sep, 2010

4 commits

  • This patch replace all the lock functions with the irq safe variant.
    The ns2_led_{set,get}_mode() functions must be safe in all context.

    For example, the trigger timer call led_set_brightness() in a softirq
    context.

    Signed-off-by: Simon Guinot
    Signed-off-by: Nicolas Pitre

    Simon Guinot
     
  • Signed-off-by: Eric Miao
    Acked-by: Saeed Bishara
    Signed-off-by: Nicolas Pitre

    Eric Miao
     
  • When using simultaneously the two DMA channels on a same engine, some
    transfers are never completed. For example, an endless lock can occur
    while writing heavily on a RAID5 array (with async-tx offload support
    enabled).

    Note that this issue can also be reproduced by using the DMA test
    client.

    On a same engine, the interrupt cause register is shared between two
    DMA channels. This patch make sure that the cause bit is only cleared
    for the requested channel.

    Signed-off-by: Simon Guinot
    Tested-by: Luc Saillard
    Acked-by: Saeed Bishara
    Signed-off-by: Nicolas Pitre

    Simon Guinot
     
  • The support for the 2 pcie port of the 6282 has broken i/o port by switching
    *_IO_PHYS_BASE and *_IO_BUS_BASE. In fact, the patches reintroduced the same
    bug solved by commit 35f029e2514be209eb0e88c7d927f3bcc42a5cc2.
    So, I'm adding back *_IO_BUS_BASE in resource declaration and fix definition
    of KIRKWOOD_PCIE1_IO_BUS_BASE. With this change, the xgi card on my t5325 is
    working again.

    Signed-off-by: Arnaud Patard
    Acked-by: Saeed Bishara
    Signed-off-by: Nicolas Pitre
    Cc: stable@kernel.org

    Arnaud Patard
     

19 Sep, 2010

3 commits

  • Jonathan Cameron reports that when using the environment
    variable KCONFIG_CONFIG, he encounters this error:

    make[2]: *** No rule to make target `.config', needed by `arch/arm/boot/compressed/vmlinux.lds'

    Reported-by: Jonathan Cameron
    Signed-off-by: Russell King

    Russell King
     
  • ARMv7 onwards requires that there are no aliases to the same physical
    location using different memory types (i.e. Normal vs Strongly Ordered).
    Access to SO mappings when the unaligned accesses are handled in
    hardware is also Unpredictable (pgprot_noncached() mappings in user
    space).

    The /dev/mem driver requires uncached mappings with O_SYNC. The patch
    implements the phys_mem_access_prot() function which generates Strongly
    Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and
    Normal Noncacheable (writecombine) if O_SYNC.

    Signed-off-by: Catalin Marinas
    Signed-off-by: Russell King

    Catalin Marinas
     
  • 5cfc8ee0bb51 (ARM: convert arm to arch_gettimeoffset()) marked all of
    at91 AND at91x40 as needing ARCH_USES_GETTIMEOFFSET, and hence no high
    res timer support / accurate clock_gettime() - But only at91x40 needs it.

    Cc: stable@kernel.org
    Signed-off-by: Peter Korsgaard
    Acked-by: John Stultz
    Acked-by: Jean-Christophe PLAGNIOL-VILLARD
    Signed-off-by: Russell King

    Peter Korsgaard
     

17 Sep, 2010

19 commits