23 Feb, 2017
40 commits
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We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC.
And this lvds2, along with lvds1, can be used to provide external clock source
to the internal pll, such as pll4_audio and pll5_video.So This patch mainly adds the lvds2 to the clock tree and fix its relationship
with pll4 accordingly.Signed-off-by: Shengjiu Wang
(cherry picked from commit f9cfc11cf8628bd01efda611074131bfa323a120) -
enable imx6qp pcie support
Signed-off-by: Richard Zhu
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enable imx6sx pci support
Signed-off-by: Richard Zhu
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The code reads the default voltage selector from its register.
If the default voltage selector is 0 which results in faulty
behaviour of this regulator driver.This patch sets a default voltage selector for vddpcie-phy if
it is not set in the register.Signed-off-by: Richard Zhu
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As thermal sensor alarm function needs PLL3 to be always on, but low power
idle needs all PLLs to be off, they are exclusive. Low power idle is only enabled
when system staying at low bus mode which means the overall system power consumption
is NOT high, thermal alarm function can be disabled in this mode to allow low power
idle to be entered, and thermal sensor will still use polling mechanism to monitor
the system temperature. Add busfreq notify to achieve this goal.
(this patch is copied from commit dd3d1e6c6ff0)Signed-off-by: Bai Ping
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During suspend/ressume, when cpufreq driver try to increase
Voltage/freq, it needs to control I2C/SPI to communicate with
external PMIC to adjust voltage, but these I2C/SPI devices may
be already suspended, to avoid such scenario, we adjust increase
cpufreq to highest setpoint before suspend.As this pm notification's updating cpu policy may work together
with cpufreq governor, both of them may call set_target at same
time, so we need to add mutex lock to prevent this scenario,
otherwise, the clock use count will be wrong.Signed-off-by: Anson Huang
Signed-off-by: Robin Gong
Signed-off-by: Bai Ping
(cherry picked from commit 9f5158fd0fd6e11e2f69cf975d3843cf6cc84048) -
for i.MX6SX, according to the latest datasheet, added a 198MHz setpoint in cpufreq driver.
The 198MHz setpoint is NOT enough to support playing mp3,the system will stay at a higher
setpoint and high_bus_mode. So when having a setpoint lower than 396MHz, make sure when
the cpufreq is at 396MHz or lower, the busfreq is always in low_bus_mode to save more power.Signed-off-by: Bai Ping
(cherry picked from commit 3ba9548200ffb2c85111dd84946046ae0c7b09c4) -
Normally, the system is booting up with higher cpufreq. In the
cpufreq set_target_index we will release the high bus mode if
the target cpu frequency is the lowest. It will release the high
bus mode and dcrease the high_bus_count.This will lead to a wrong
release of high bus mode. So, in the cpufreq_init function, if the
original frequency is not the lowest, we need request high busfreq.Signed-off-by: Bai Ping
(cherry picked from commit 7df8887a6ddac148d33cd583da31ec72d0ba07da) -
Request high bus frequency before scaling up the CPU frequency
and release high bus frequency after scaling down the CPU frequencyDoing so makes a balance between high performance and lower power
consumption.Signed-off-by: Bai Ping
(cherry picked from commit 35c91da2591a70858d5eec184c662851e39082d2) -
Initial port of the mxc V4L2 capture driver.
Baseline copied from imx_3.14.y branch:Signed-off-by: Sandor Yu
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If anyone calls v4l2_async_notifier_unregister() recursively from
device_release_driver(), code will deadlock at list_lock, so unlock
list_lock when device_release_driver() called.Signed-off-by: Sandor Yu
(cherry picked from commit f0b54df4d1b58f8f6608e1b08a80a5acb8cc12ea) -
This reverts commit 5cf6f7f327c95f09be859889be39e78950516556.
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This parameter bypass count is used to make sure the mipi
dsi be initialized correctly without any display error.
In the mipi dsi initialization, it requires the first
two parameter setting operations should be done really.Signed-off-by: Fancy Fang
(cherry picked from commit 969122c2f4363dee4cf489b87984c4d85dcd89ce)Conflicts:
drivers/video/mxsfb.c -
Initialize local variable 'i' to 0, otherwise may fall into wrong
code path. The issue come with commit 757ff4b89.Signed-off-by: Robin Gong
(cherry picked from commit 186f722c260279e21e05e4b13c9cc4d8348ae370) -
Pfuze200 only provide one power supply for VDDARM_IN and VDDSOC_IN,
for ldo-bypass mode, we have to pretend they are different regulators
otherwise regulator famework will refuse update voltage.Signed-off-by: Robin Gong
(cherry picked from commit 1b41ab90288b2accd710f8852c11753007749e4a) -
Most of i.mx6 and i.mx7 board need to support WDOG_B reboot to workaroud some
issues such as ldo-bypass, QSPI-NOR boot issue. Please enable 'fsl,wdog_b'
property if you want to use WDOG_B reboot(trigger PMIC reboot).Signed-off-by: Robin Gong
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This patch cherry-pick from below:
"ENGR00317981: regulator: anatop: force vddpu to use same voltage level as vddsoc"The anatop on i.MX6 requires that vddpu use the same voltage level as
vddsoc. It's a quick hacking to force the check whenever vddpu is
about to be enabled.Signed-off-by: Shawn Guo
Signed-off-by: Robin Gong
(cherry picked from commit ab0c52e019cacc89aec3dbb104360b4715d49796)Conflicts:
drivers/regulator/anatop-regulator.c -
Fixed wrong symbols of GPU in mxc/Makefile.
Date Sep 22, 2015
Signed-off-by: Shawn Xiao
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The pm power's usage_count should be first added by
one before putting it into suspend state. Otherwise
the usage_count will be negative and the power cannot
be put into suspend state correctly.Signed-off-by: Fancy Fang
(cherry picked from commit a48460b41399112f5d3ae03b30e3f9e885346ff7)Conflicts:
drivers/video/mxsfb.c -
The reason for this issue is that, on imx6sx platform, there is a display mix
to control the display modules(including lcdif) power on/off. When the fb
driver calls the 'pm_runtime_put_sync_suspend()', the display mix will be
powered down. And at this moment, all the register settings for lcdif always
have no effects. So the pm_runtime calling points in mxsfb driver should be
optimized to avoid this kind of cases.Signed-off-by: Fancy Fang
(cherry picked from commit 3b85eb989c89fb1c6d08215e435d72ab175e4e1e)Conflicts:
drivers/video/mxsfb.c -
As streamoff/streamon will reset all buffer list, video output count should
be reset to zero. Or timer will get wrong schedule time if input buffer time
stamp is 0.Signed-off-by: Song Bing b06498@freescale.com
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Forward imx_3.14.y mxc video output drivers to 4.1 kernel.
The priv field of v4l2_pix_format is used to expand colorspace,
and can not use to pass IPU input crop size.
Add private IOCTL VIDIOC_S_INPUT_CROP and VIDIOC_G_INPUT_CROP
to pass input crop size.Signed-off-by: Sandor Yu
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Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platformsEnalbe the msi pcie ep rc on it.
Test howto:
- Enable CONFIG_PCI_MSI=y, when rebuild the rc/ep images- EP side(console command and kernel message):
root@imx6sxsabresd:~# ./memtool -32 =0
Writing 32-bit value 0x0 to address- RC side(console command and kernel message):
root@imx6sxsabresd:~# cat /proc/interrupts | grep MSI
384: 1 PCI-MSINote:
imx6q msi_addr 0x01ff_8000
imx6sx msi_addr 0x08ff_8000
imx7d msi_addr 0x4ffc_0000Signed-off-by: Richard Zhu
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Regarding to the limitation of the iMX ADAP(pcie connector),
only imx7d 12x12 arm2 board is used to verify the pcie
ep/rc validation system on imx7d platformshw setup:
* two imx boards, one is used as pcie rc, the other is used
as pcie ep. Connected by fsl pcie adap adaptor.sw setup:
* when build rc image, make sure that
CONFIG_IMX_PCIE=y
# CONFIG_EP_MODE_IN_EP_RC_SYS is not set
CONFIG_RC_MODE_IN_EP_RC_SYS=y
* when build ep image
CONFIG_IMX_PCIE=y
CONFIG_EP_MODE_IN_EP_RC_SYS=y
# CONFIG_RC_MODE_IN_EP_RC_SYS is not setfeatures:
* set-up link between rc and ep by their stand-alone
ref clk running internally.* in ep's system, ep can access the reserved ddr memory
(default address:0x4000_0000 on imx6q sd board, and
0xb000_0000 on imx6sx sdb and imx7d arm2 boards) of
pcie rc's system, by the interconnection between pcie
ep and pcie rc.* add the configuration methods in the ep side, used to
configure the start address and the size of the reserved
rc's memory window.
- cat /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_info
- echo 0x41000000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_start_set
- echo 0x200000 > /sys/devices/soc0/soc.1/1ffc000.pcie/rc_memw_size_set* provide one example, howto configure the bar# and so on,
when pcie ep emaluates one memory ram ep device* setup one new outbound memory region at rc side, used
to let imx pcie rc can access the memory of imx pcie ep
in imx pcie rc ep validation system.
- set the default address of the ddr memory to be 0x4000_0000
on imxq sd board, and 0xb000_0000 on imx6sx sdb and imx7d
arm2 boards.NOTE:
* boot up ep platform firstly, then boot up rc platform.
* make sure that mem=768M is contained in the kernel command line,
since the start address of the upper 256mb of the 1g ddr mem is
reserved to do the pcie ep rc access operations in default.Test howto of the RC access memory of EP on imx6q sd platforms.
step1:
EP side:
1.1:
echo > /sys/devices/.../pcie/ep_bar0_addr1.2:
memtool -32 4
E
Reading 0x4 count starting at address 0x40000000: 6FE9E9F6 7583FBB9 39EAEFEA FBDCFD78
step2:
RC side:
memtool -32 =58D454DA
memtool -32 =7332095Bstep3:
EP side:
memtool -32 4
E
Reading 0x4 count starting at address 0x40000000: 58D454DA 7332095B 39EAEFEA FBDCFD78
Signed-off-by: Richard Zhu
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- enable pcie functions on imx7d platforms
- grst/brst should be asserted/de-asserted during resume,
since the pcie power would be cut off automatically by HW
during system suspend/resumeSigned-off-by: Richard Zhu
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- move "program correct class for RC" from dw_pcie_host_init()
to dw_pcie_setup_rc(). since this is RC setup, it's
better to contained in dw_pcie_setup_rc function.
Then, RC can be re-setup really by dw_pcie_setup_rc().
- add one store/re-store msi cfg functions. Because that
pcie controller maybe powered off during system suspend,
and the msi data configuration would be lost.
these functions can be used to store/restore the msi data
and msi_enable during the suspend/resume callback.Signed-off-by: Richard Zhu
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This reverts commit b71c99801e18eb172ae34851daf25044a3bf644a.
Signed-off-by: Oliver Brown
(cherry picked from commit 5c74966c0e7deb0ac84b3fa8a84c6c942e7d434f)Conflicts:
drivers/media/v4l2-core/v4l2-compat-ioctl32.c
include/media/v4l2-subdev.h -
1. Upstream 5.0.11p7 driver to kernel
2. Add the GPU configuration to imx6q.dtsi
3. Remove IRQF_DISABLED in GPU driver
The IRQF_DISABLED has been removed from 4.1.0 kernel. To accomodate with
the change, add version check logic and use 0x0 instead of IRQF_DISABLED
from 4.1.0 kernel on.4. Convert file->f_dentry->d_inode to file_inode() in GPU driver
The file struct has changed since 3.19. Changed the usage in GPU driver
too.5. Add version check for CONFIG_PM_RUNTIME
The CONFIG_PM_RUNTIME will never be used in 4.1.0 kernel. Add version
check to avoid calling it in GPU driver.Signed-off-by: Shawn Xiao
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No need to alloc bd for hdmi audio, and the period len of hdmi audio is
0, so add constraint for it.And correct per_address and per_address2 for hdmi audio.
Signed-off-by: Zidan Wang
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Enable devfreq cooling to trigger GPU freq change when
hot trip is reached.Make sure thermal driver loaded after cpufreq is loaded,
otherwise, cpu_cooling will not get valid cpufreq table,
hence cpu_cooling will be not working.Signed-off-by: Bai Ping
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add .get_trend callback to determine the thermal raise/fall trend,
when the temp great than a threshold, drop to the lowest trend
(THERMAL_TREND_DROP_FULL).Signed-off-by: Bai Ping
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This pacth re-write part of the code the support i.MX6 and i.MX7
in thermal driver. the TEMPMON module in i.MX6 and i.MX7 can provide
the same funtion, but has different register offset and bitfield define.Signed-off-by: Bai Ping
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On i.MX6SL, we must make sure ARM:IPG clock ratio is within 12:5 when entering
wait mode. If the system is in low_bus_freq_mode, the IPG is at 12MHz
according the busfreq code. So the max rate of ARM is 28.8MHz when entering
wait mode. As there is no way run at this clk rate, so set ARM to run from
24MHz OSC.Signed-off-by: Bai Ping
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Add busfreq support for i.MX6SL SOC. we support three
busfreq mode (high_bus_freq_mode/low_bus_freq_mode and
audio_bus_freq_mode).Signed-off-by: Bai Ping
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The 'PLL1_SYS' and 'PLL1_SW' clks are used by the cpufreq
driver to do dynamic frequency changing procedure.The 'CLK_SET_PARENT_GATE' should not be set for 'PLL1_SW'
clk, this clock's prepare_count is not zero all the time.change the clk type of 'PLL1_SYS' to fixed_factor. due to
the hardware limit, when changing the ARM_PODF. This clock's
output should not be gated.Signed-off-by: Bai Ping
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According to the latest reference manual, the default AXI clock rate
should be 264MHz. Soucre AXI/AHB from pll2_bus to get the required
clock rate.Signed-off-by: Bai Ping
(cherry picked from commit d7560da7baee7a14ecb33d51182bbdc485ee6d7d) -
send a message to our remote processor, and tell remote
processor about this channelSigned-off-by: Richard Zhu
(cherry picked from commit 2708c004a60c5b6da020803ee9291b83984d4a65) -
AXI clk should be always enabled, as many peripheral
devices need this clk to be on, especially for busfreq,
AXI podf change needs AXI clk and its parent on.Signed-off-by: Anson Huang
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Forward imx_3.14.y IPU and display drivers to 4.1 kernel.
This includes IPU core driver, display driver, LDB and HDMI driver.Signed-off-by: Sandor Yu
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When VPU is running at 352MHz, SOC/PU voltage need to be
at 1.25V for 396/792MHz setpoint, as 396M setpoint is
removed, so only increase 792M setpoint's voltage.Signed-off-by: Anson Huang
