23 Feb, 2017
40 commits
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Document the gpmi-nand compatibility for i.MX6ULL
Signed-off-by: Han Xu
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support NAND on imx6ull
Signed-off-by: Han Xu
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Support NAND on imx6ull
Signed-off-by: Han Xu
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Correct pxp clock settings according to the commit
'MLK-12669-2 dma: pxp-v3: add 'ipg' and 'axi' clocks'.Signed-off-by: Fancy Fang
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The pwm3 and otg1 share the same pin 'GPIO1_IO04'. And default,
the pin is used for otg1. So create a new dts file to solve
this conflict.Signed-off-by: Fancy Fang
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Add 'ipg' and 'axi' clocks for pxp which should
be used to control runtime power managments.Signed-off-by: Fancy Fang
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The pxp require two clocks to enable when it works, and
they are 'ipg' and 'axi' clocks. Besides, the two clocks
share the same CCGR to control clock gating.Signed-off-by: Fancy Fang
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SRTC needs to be kept enabled during system poweroff,
SNVS_LP control register bit 0 SRTC_ENV must be set
to enable RTC, for software poweroff, kernel just
read the register offset and value from dtb and write
to SNVS_LP control register to poweroff system, need
to make sure bit 0 SRTC_ENV is set to enable RTC during
system poweroff.Previous setting did NOT enable it which will cause
RTC stop running if using software poweroff.Signed-off-by: Anson Huang
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Need to make sure build pass with single SOC
config, in current build for single SOC config,
if both SOC_IMX7D and SOC_IMX6SX are NOT selected,
below build error will occur, add MU module
config to fix this build issue.LD init/built-in.o
arch/arm/mach-imx/built-in.o: In function `busfreq_probe':
:(.text+0x5370): undefined reference to `imx_mu_lpm_ready'
arch/arm/mach-imx/built-in.o: In function `bus_freq_pm_notify':
:(.text+0x5d50): undefined reference to `imx_mu_lpm_ready'
:(.text+0x5d68): undefined reference to `imx_mu_lpm_ready'
make: *** [vmlinux] Error 1Signed-off-by: Anson Huang
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We've got more than 24 channels defined in ipu_channel_t, which causes
potential overrun on array ipu->sec_chan_en and ipu->thrd_chan_en.
This patch enlarges the array size to IPU_MAX_CH(32) to fix this issue.This issue is reported by Coverity:
Out-of-bounds read (OVERRUN)
overrun-local: Overrunning array ipu->sec_chan_en of 24 bytes at byte offset
25 using index channel >> 24 (which evaluates to 25).
if ((ipu->sec_chan_en[IPU_CHAN_ID(channel)]) &&
((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM) ||
(channel == MEM_VDI_PRP_VF_MEM))) {Out-of-bounds read (OVERRUN)
overrun-local: Overrunning array ipu->thrd_chan_en of 24 bytes at byte offset
25 using index channel >> 24 (which evaluates to 25).
if ((ipu->thrd_chan_en[IPU_CHAN_ID(channel)]) &&
((channel == MEM_PP_MEM) || (channel == MEM_PRP_VF_MEM))) {
thrd_dma = channel_2_dma(channel, IPU_ALPHA_IN_BUFFER);Signed-off-by: Liu Ying
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Enable i.MX6ULL in imx_v7_defconfig.
Signed-off-by: Bai Ping
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Enable DSM for i.MX6ULL, UART_UBRC is a read-only
register, writting it will cause external abort,
so skip save/restore for this register.Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
Add suspend/resume support for i.MX6ULL.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
Add dts file for i.MX6ULL DDR3 ARM2 board.
Signed-off-by: Peng Fan
Signed-off-by: Bai Ping -
Add dtsi file for i.MX6ULL.
Signed-off-by: Peng Fan
Signed-off-by: Bai Ping -
The general architecture of i.MX6ULL is same as i.MX6UL. So
most of the clock driver code of i.MX6UL can be reused by
i.MX6ULL.Signed-off-by: Peng Fan
Signed-off-by: Bai Ping -
Add MSL code support for i.MX6ULL.
Signed-off-by: Peng Fan
Signed-off-by: Bai Ping -
When CONFIG_MMC=m, compile error shows up
ERROR: "of_alias_max_index" [drivers/mmc/core/mmc_core.ko] undefined!
ERROR: "mmc_get_reserved_index" [drivers/mmc/card/mmc_block.ko] undefined!
ERROR: "mmc_first_nonreserved_index" [drivers/mmc/card/mmc_block.ko] undefined!
make[1]: *** [__modpost] Error 1
make: *** [modules] Error 2
make: *** Waiting for unfinished jobs....This patch export the upper three symbol for module runtime load.
Signed-off-by: Haibo Chen
(cherry picked from commit 3b2520f17d427b8fa8db37a6d9a4311f20c29036) -
GPU 3D clock will still enable/disable when video playback,
actually there is no 3D usage, to saving power we should
avoid 3D clock enable/disable. This patch optimize event
synchronization by not pass signal/sync_point to gpu when
current gcoHARDWARE is already sync'ed GPU and no command
buffer required.Date: Apr 13, 2016
Signed-off-by: Richard Liu
Signed-off-by: Meng Mingming -
In the OCOTP fuse map, the speed grading[1:0] define the MAX
CPU speed the chip can run. The detailed definition is below:
2b'00: Reserved;
2b'01: 528000000Hz;
2b'10: 696000000Hz;
2b'11: Reserved;We need to disable the illegal setpoints according to the fuse map.
Signed-off-by: Bai Ping
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According to the latest datasheet(Rev. 0, 12/2015),
When the chip is run at LDO enabled mode, the highest
setpoint can be set to 700MHz in overdrive mode.Signed-off-by: Bai Ping
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On i.MX6UL EVK board, we use a external GPIO DC regulator to control
the VDD_ARM_SOC_IN voltage, if default voltage is 1.4V when the system
is bootup. Per design team, when the highest setpoint freq is not
bigger than 528MHz, we can decrease this regulator voltage to 1.3V.
On i.MX6UL TO1.1, we add a 700MHz setpoint. When the highest setpoint
freq is 700MHz, the DC regulator should be at 1.4V to to cover the IR
drop.Signed-off-by: Bai Ping
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This patch removes boilerplate code to register clocks for two DIs of one IPU.
Also, the char strings for storing the pixel clock parent names are wrongly
placed in the kernel rodata section, which will be overwritten when clocks
are registered. This patch moves the problematic strings to stack. Since
clk_register() will cache his own version from non-kernel-rodata space, this
may fix the issue.Signed-off-by: Liu Ying
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i.MX7d MAC1_ADDR fuse offset address is 0x640, i.MX6q/dl/sx/ul
MAC1_ADDR fuse offset address is 0x620. Correct it for i.MX7d,
otherwise read un-correct MAC address.Signed-off-by: Fugang Duan
(cherry picked from commit:74ee5313534dd9453601f4428c4916d46405669f) -
missed the brackets for bch legacy support, which leads the large oob
nand bch setting to wrong path.Signed-off-by: Han Xu
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document the new option for legacy bch geometry support.
Conflicts:
Documentation/devicetree/bindings/mtd/gpmi-nand.txtSigned-off-by: Han Xu
(cherry picked from commit c1c24ecd24cb808e825eb13a3e3d016c283322cc) -
Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Conflicts:
drivers/mtd/nand/gpmi-nand/gpmi-nand.hSigned-off-by: Han Xu
(cherry picked from commit 4d28b1693905526558892d40525763e6bc4469e4) -
Remove the pre-processing and post-processing table. use proc_autosel()
to select proper parameters.
Unify the supported input and output rate.Signed-off-by: Shengjiu Wang
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ov5647 mipi camera sensor is replaced by ov5640
on imx7D SDB RevB board.Signed-off-by: Sandor Yu
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Combine csi image setting function for 32-bit,16-bit,8-bit format.
For parallel 8-bit sensor input, when bit per pixel is 16,
csi image width should been doubled.
But for mipi input, the csi image width and height should align
with mipi whatever data width.Signed-off-by: Sandor Yu
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-Support no power and reset pins platform.
-Remove specific power and reset pin setting for ov5640 daughter card.
-Put sensor in software power down state when streamoff.
-Remove unsupported video modes, keep 640x480, 720x480, 720p, 1080p 30fps
video modes in driver.Signed-off-by: Sandor Yu
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During the read of NOR, the kernel actually calls the inline_map_copy_from()
to read the data out. And inline_map_copy_from() will use the memcpy_fromio()
to do the real job.The memcpy_fromio macro maps _memcpy_fromio() in the current code.
But the _memcpy_fromio() will use readb() to do the copy work one byte
by one byte. This makes the read performance of NOR very slow(about 2~3MB/s).A similiar discussion could be found in:
http://lists.infradead.org/pipermail/linux-arm-kernel/2009-November/003860.htmlThis patch replace the memcpy_fromio with memcpy which is optimized by the
kernel.The following is the result from mtd_speedtest with M29W256GL7AN6E:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: not NAND flash, assume page size is 512 bytes.
mtd_speedtest: MTD device size 4194304, eraseblock size 131072, page size 512,
count of eraseblocks 32, pages per eraseblock 256, OOB size 0
mtd_speedtest: testing eraseblock write speed
mtd_speedtest: eraseblock write speed is 845 KiB/s
mtd_speedtest: testing eraseblock read speed
mtd_speedtest: eraseblock read speed is 19504 KiB/s
mtd_speedtest: testing page write speed
mtd_speedtest: page write speed is 845 KiB/s
mtd_speedtest: testing page read speed
mtd_speedtest: page read speed is 19140 KiB/s
mtd_speedtest: testing 2 page write speed
mtd_speedtest: 2 page write speed is 846 KiB/s
mtd_speedtest: testing 2 page read speed
mtd_speedtest: 2 page read speed is 19320 KiB/s
mtd_speedtest: Testing erase speed
mtd_speedtest: erase speed is 233 KiB/s
mtd_speedtest: Testing 2x multi-block erase speed
mtd_speedtest: 2x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 4x multi-block erase speed
mtd_speedtest: 4x multi-block erase speed is 224 KiB/s
mtd_speedtest: Testing 8x multi-block erase speed
mtd_speedtest: 8x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 16x multi-block erase speed
mtd_speedtest: 16x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 32x multi-block erase speed
mtd_speedtest: 32x multi-block erase speed is 225 KiB/s
mtd_speedtest: Testing 64x multi-block erase speed
mtd_speedtest: 64x multi-block erase speed is 224 KiB/s
mtd_speedtest: finished
=================================================(cherry-picked from: f1e5914ffd82d5326cbd30507d4f37d02a0da099)
Signed-off-by: Huang Shijie
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Add missing .release callback in file_operations of vidmem_operations in order to release the allocated memory.
Date: Mar 18, 2016
Signed-off-by: Yuchou Gan -
The patch removes the dependence between cache flush operation and node.
Node is not used anymore when flush cache. Cache flush can work with only
logical address passed into underlying functions does not need physical
address.Signed-off-by: Richard Liu
(cherry picked from commit ad65770512d2baeb45f5d0622d985f9856b7cc1e) -
It has converted sync to fence api in kernel_imx/drivers/staging/android/sync.h,
so make it done in gpu driver to match kernel.Signed-off-by: Meng Mingming
Signed-off-by: Richard Liu
(cherry picked from commit d69c57557a2ef782d0daa617a30945f41a608fd5) -
when do vte test it meets follow dump in small probability.
Add against-0 check to resovle this.$ v4l_emma.sh 1 1
$ v4l_emma.sh 1 9------------[ cut here ]------------
: /dev/video1 Set PARM sucessfulWARNING: CPU: 0 PID: 1123 at /home/bamboo/build/4.1.X-1.0.0_ga/fsl-
imx-fb/temp_build_dir/build_fsl-imx-fb/tmp/work-shared/imx6qdlsolo/kernel-source/mm/page_alloc.c:266
5 __alloc_pages_nodemask+0x3c8/0x894()
ly
v4l_capture_testapp 0 TINModules linked in:FO : /dev/video1 input formatti mx6s_captureng pass
v4l_capture_testapp 0 ov5640_camera TINFO : PRP_ENC_ON_D gpRGBcon evbugv_buf malloc pass!CPU: 0 PID: 1123 Comm: v4l2_capture_em Not tainted 4.1.8-1.0.0+g87e6c2f #1
Hardware name: Freescale i.MX6 Ultralite (Device Tree)
[] (unwind_backtrace) from [] (show_stack+0x10/0x14)
[] (show_stack) from [] (dump_stack+0x84/0xc4)
[] (dump_stack) from [] (warn_slowpath_common+0x80/0xb0)
[] (warn_slowpath_common) from [] (warn_slowpath_null+0x1c/0x24)
[] (warn_slowpath_null) from [] (__alloc_pages_nodemask+0x3c8/0x894)
[] (__alloc_pages_nodemask) from [] (__dma_alloc_buffer.isra.3+0x2c/0x84)
[] (__dma_alloc_buffer.isra.3) from [] (__alloc_remap_buffer.isra.6+0x1c/0x8c)
[] (__alloc_remap_buffer.isra.6) from [] (__dma_alloc+0x1fc/0x228)
[] (__dma_alloc) from [] (arm_dma_alloc+0x8c/0xa0)
[] (arm_dma_alloc) from [] (vb2_dc_alloc+0x68/0x100)
[] (vb2_dc_alloc) from [] (__vb2_queue_alloc+0x134/0x4d0)
[] (__vb2_queue_alloc) from [] (__reqbufs.isra.17+0x1a8/0x304)
[] (__reqbufs.isra.17) from [] (__video_do_ioctl+0x2b0/0x324)
[] (__video_do_ioctl) from [] (video_usercopy+0x1b8/0x480)
[] (video_usercopy) from [] (v4l2_ioctl+0x118/0x150)
[] (v4l2_ioctl) from [] (do_vfs_ioctl+0x3e8/0x608)
[] (do_vfs_ioctl) from [] (SyS_ioctl+0x34/0x5c)
[] (SyS_ioctl) from [] (ret_fast_syscall+0x0/0x3c)
---[ end trace 55ed68f89eca4805 ]---
mx6s-csi 21c4000.csi: dma_alloc_coherent of size 0 failedSigned-off-by: Robby Cai
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Q901 (IRLML6401) is p-channel MOSET, need set pin1 (LCD_nPWREN) to low
to let pin3 output be 3V3. Normally when pin1 is high, then pin3
output should be gated. It was working previously due to some leakage.
Correct the enable logic from the software viewpoint.Signed-off-by: Robby Cai
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After the suspend/resume, hw_params may be called in bias_level is not
BIAS_ON, then the PLL is not disable/enabled, if the sample rate is
changed, the output clock is not correct.Signed-off-by: Shengjiu Wang
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After suspend and resume, the wm8960 codec will change the state from
BIAS_OFF to BIAS_ON, in this time, the hw_free is called, the PLL will be
diabled, and next instance is started in rapid sequence, hw_params is called
But PLL is not enabled, because the bias state is not BIAS_ON.As PLL is disabled in BIAS_ON->BIAS_STANDBY, so don't need to disable pll
in hw_free of machine driver.Signed-off-by: Shengjiu Wang
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The head list may be corrupted when two requests from
the same 'pxp_chan' are issued sequentially. So change
the issue_pending function to strictly serialized the
requests to avoid this kind of issue.Signed-off-by: Fancy Fang
