23 Jul, 2019
1 commit
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Fix build warning when CONFIG_PM_SLEEP=n, the warning message is:
drivers/irqchip/irq-imx-irqsteer.c:104:13: warning: ‘imx_irqsteer_init’ defined but not used [-Wunused-function]
static void imx_irqsteer_init(struct irqsteer_irqchip_data *irqsteer_data)
^~~~~~~~~~~~~~~~~Signed-off-by: Clark Wang
31 May, 2019
1 commit
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Instead of just raising irq0 for all the cores, we mask the irq0 for all the
non-target cores, this way waking up only the core we want. All of this
is done now in TF-A.Also, since this new workaround doesn't need the IOMUX_GPR1 register here
in kernel, the IOMUX_GPR reg entry inside the gic dts node can be removed.In order for this to work, the following commit is needed in TF-A:
0e91ff59720d0756 ("MLK-21399 plat: imx8mq: gpc: Workaround for ERR11171")Signed-off-by: Abel Vesa
Reviewed-by: Leonard Crestez
18 Apr, 2019
14 commits
-
Upstream rejected ARCH_MXC_ARM64 in favor of defining ARCH_MXC for
arm64 so the current condition is never enabled.Copy upstream Kconfig instead for irqsteer and intmux.
Signed-off-by: Leonard Crestez
-
Fix iMX8MQ workaround to be specific to that
machine.Signed-off-by: Nitin Garg
(cherry picked from commit 5fc3246190546c455f47fa3094ee717bd84a167c) -
On i.MX8MQ, when the CPU core is in power down state,
the IPI can NOT wakeup the core anymore(ERR011171), so using the
external IRQ32 to wakeup the core in power down idle
state successfully.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit d3244056f749c0ce590a671e215eb39fff336fc2) -
Fixes: a2e6a7833495 (MLK-16136-9 irqchip: imx-irqsteer: adjust irq config
via 'endian')This patch fixes mask register offset calculation, when endian is not
default value 0 (i.e imx8mq).Signed-off-by: Antoine Bouyer
Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel -
Add runtime pm to manage irqsteer clock and its power domain in system
idle and suspend status to save power.Signed-off-by: Fugang Duan
Signed-off-by: Frank Li
Tested-by: Guoniu.Zhou
Reviewed-by: Frank Li
Signed-off-by: Arulpandiyan Vadivel -
Once irqsteer controller is power off during suspend, the registers
are lost, it should restore the registers after resume back.BuildInfo:
- SCFW a479ff78, IMX-MKIMAGE ff9860c5, ATF 923651a
- U-Boot 2017.03-00691-g96cf020Signed-off-by: Fugang Duan
Tested-by: Pandy.gao
Acked-by: Pandy.gao
Signed-off-by: Arulpandiyan Vadivel -
Irqsteer block only supports level interrupts.
(BuildInfo: SCFW 3e70523d, IMX-MKIMAGE 0, ATF 0)
Signed-off-by: Seb Laveze
Signed-off-by: Fugang Duan
Reviewed-by: Richard Zhu
Signed-off-by: Arulpandiyan Vadivel -
Fix the offset of CHANIPR register address. Document is KL28Z
reference manualSigned-off-by: Shengjiu Wang
Signed-off-by: Arulpandiyan Vadivel -
Change the irq configurations with adding endianness
determination for different platforms which may choose
different kinds of endianess.Signed-off-by: Fancy Fang
Signed-off-by: Arulpandiyan Vadivel -
Correct several macro definitions related with irqsteer
to avoid incorrect expression calculation due to operators
priority.Signed-off-by: Fancy Fang
Signed-off-by: Arulpandiyan Vadivel -
The intmux module is used to output internal interrupt in subsystem
to system with 32-to-8 configuration. It has several multiplex
channels depends on system. intmux is introduced in KL28Z reference
manual.Signed-off-by: Shengjiu Wang
Signed-off-by: Arulpandiyan Vadivel -
The type of irqstat in irqsteer_irqchip_data unsigned long, actually
it needs to be 32bits width, so use unsigned int.And use sizeof(irqsteer_data->irqstat[0]), instead of 4 when alloc
memory for irqsteer_data.for_each_set_bit needs the second param type is unsigned long *, so
cast the irqsteer_data->irqstat to unsigned long *, this is safe here.Signed-off-by: Peng Fan
Signed-off-by: Arulpandiyan Vadivel -
Some subsystems have lpcg sw_bit to control the ipg_clk to LIS,
so add the ipg clock for the module.Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel -
The IrqSteer module redirects/steers the incoming interrupts to output
interrupts of a selected/designated channel as specified by a set of
configuration registers.NXP i.MX8x chips integrate IrqSteer controller for some DSC to share irq
line for all modules in the subsystem which can reduce the IRQ lines
connected to the parent interrupt controller GIC, so IrqSteer irqchip
acts as the second irq domain in the system.Signed-off-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel
27 Mar, 2019
1 commit
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commit 89dc891792c2e046b030f87600109c22209da32e upstream.
The lpi_range_list is supposed to be sorted in ascending order of
->base_id (at least if the range merging is to work), but the current
comparison function returns a positive value if rb->base_id >
ra->base_id, which means that list_sort() will put A after B in that
case - and vice versa, of course.Fixes: 880cb3cddd16 (irqchip/gic-v3-its: Refactor LPI allocator)
Cc: stable@vger.kernel.org (v4.19+)
Signed-off-by: Rasmus Villemoes
Signed-off-by: Marc Zyngier
Signed-off-by: Greg Kroah-Hartman
24 Mar, 2019
2 commits
-
commit 33517881ede742107f416533b8c3e4abc56763da upstream.
Using the irq_gc_lock/irq_gc_unlock functions in the suspend and
resume functions creates the opportunity for a deadlock during
suspend, resume, and shutdown. Using the irq_gc_lock_irqsave/
irq_gc_unlock_irqrestore variants prevents this possible deadlock.Cc: stable@vger.kernel.org
Fixes: 7f646e92766e2 ("irqchip: brcmstb-l2: Add Broadcom Set Top Box Level-2 interrupt controller")
Signed-off-by: Doug Berger
Signed-off-by: Florian Fainelli
[maz: tidied up $SUBJECT]
Signed-off-by: Marc Zyngier
Signed-off-by: Greg Kroah-Hartman -
commit 8d565748b6035eeda18895c213396a4c9fac6a4c upstream.
In current logic, its_parse_indirect_baser() will be invoked twice
when allocating Device tables. Add a *break* to omit the unnecessary
and annoying (might be ...) invoking.Fixes: 32bd44dc19de ("irqchip/gic-v3-its: Fix the incorrect parsing of VCPU table size")
Cc: stable@vger.kernel.org
Signed-off-by: Zenghui Yu
Signed-off-by: Marc Zyngier
Signed-off-by: Greg Kroah-Hartman
14 Mar, 2019
3 commits
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[ Upstream commit 2380a22b60ce6f995eac806e69c66e397b59d045 ]
Resetting bit 4 disables the interrupt delivery to the "secure
processor" core. This breaks the keyboard on a OLPC XO 1.75 laptop,
where the firmware running on the "secure processor" bit-bangs the
PS/2 protocol over the GPIO lines.It is not clear what the rest of the bits are and Marvell was unhelpful
when asked for documentation. Aside from the SP bit, there are probably
priority bits.Leaving the unknown bits as the firmware set them up seems to be a wiser
course of action compared to just turning them off.Signed-off-by: Lubomir Rintel
Acked-by: Pavel Machek
[maz: fixed-up subject and commit message]
Signed-off-by: Marc Zyngier
Signed-off-by: Sasha Levin -
[ Upstream commit 45725e0fc3e7fe52fedb94f59806ec50e9618682 ]
In the unlikely event that we cannot find any available LPI in the
system, we should gracefully return an error instead of carrying
on with no LPI allocated at all.Fixes: 38dd7c494cf6 ("irqchip/gic-v3-its: Drop chunk allocation compatibility")
Signed-off-by: Marc Zyngier
Signed-off-by: Sasha Levin -
[ Upstream commit 6479450f72c1391c03f08affe0d0110f41ae7ca0 ]
1. In current implementation, every VLPI will temporarily be mapped to
the first CPU in system (normally CPU0) and then moved to the real
scheduled CPU later.2. So there is a time window and a VLPI may be sent to CPU0 instead of
the real scheduled vCPU, in a multi-CPU virtual machine.3. However, CPU0 may have not been scheduled as a virtual CPU after
system boots up, so the value of its GICR_VPROPBASER is unknown at
that moment.4. If the INTID of VLPI is larger than 2^(GICR_VPROPBASER.IDbits+1),
while IDbits is also in unknown state, GIC will behave as if the VLPI
is out of range and simply drop it, which results in interrupt missing
in Guest.As no code will clear GICR_VPROPBASER at runtime, we can safely
initialize the IDbits field at boot time for each CPU to get rid of
this issue.We also clear Valid bit of GICR_VPENDBASER in case any ancient
programming gets left in and causes memory corrupting. A new function
its_clear_vpend_valid() is added to reuse the code in
its_vpe_deschedule().Fixes: e643d8034036 ("irqchip/gic-v3-its: Add VPE scheduling")
Signed-off-by: Heyi Guo
Signed-off-by: Heyi Guo
Signed-off-by: Marc Zyngier
Signed-off-by: Sasha Levin
06 Mar, 2019
1 commit
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[ Upstream commit c530bb8a726a37811e9fb5d68cd6b5408173b545 ]
The mbi_lock mutex is left uninitialized, so let's use DEFINE_MUTEX
to initialize it statically.Fixes: 505287525c24d ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller")
Signed-off-by: Yang Yingliang
Signed-off-by: Marc Zyngier
Signed-off-by: Sasha Levin
13 Feb, 2019
1 commit
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commit 9791ec7df0e7b4d80706ccea8f24b6542f6059e9 upstream.
On systems or VMs where multiple devices share a single DevID
(because they sit behind a PCI bridge, or because the HW is
broken in funky ways), we reuse the save its_device structure
in order to reflect this.It turns out that there is a distinct lack of locking when looking
up the its_device, and two device being probed concurrently can result
in double allocations. That's obviously not nice.A solution for this is to have a per-ITS mutex that serializes device
allocation.A similar issue exists on the freeing side, which can run concurrently
with the allocation. On top of now taking the appropriate lock, we
also make sure that a shared device is never freed, as we have no way
to currently track the life cycle of such object.Reported-by: Zheng Xiang
Tested-by: Zheng Xiang
Cc: stable@vger.kernel.org
Signed-off-by: Marc Zyngier
Signed-off-by: Greg Kroah-Hartman
31 Jan, 2019
1 commit
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commit 8208d1708b88b412ca97f50a6d951242c88cbbac upstream.
The way we allocate events works fine in most cases, except
when multiple PCI devices share an ITS-visible DevID, and that
one of them is trying to use MultiMSI allocation.In that case, our allocation is not guaranteed to be zero-based
anymore, and we have to make sure we allocate it on a boundary
that is compatible with the PCI Multi-MSI constraints.Fix this by allocating the full region upfront instead of iterating
over the number of MSIs. MSI-X are always allocated one by one,
so this shouldn't change anything on that front.Fixes: b48ac83d6bbc2 ("irqchip: GICv3: ITS: MSI support")
Cc: stable@vger.kernel.org
Reported-by: Ard Biesheuvel
Tested-by: Ard Biesheuvel
Signed-off-by: Marc Zyngier
Signed-off-by: Greg Kroah-Hartman
14 Nov, 2018
1 commit
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[ Upstream commit 7bae48b22c8d38c5cd50f52b6e15d134e2bb3935 ]
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH
as IRQ_TYPE_EDGE_RISING at the GIC.Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs")
Reported-by: Evan Green
Reviewed-by: Evan Green
Signed-off-by: Lina Iyer
Signed-off-by: Marc Zyngier
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
07 Sep, 2018
1 commit
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Commit fe8e93504ce8 ("irqchip/gic-v3-its: Use full range of LPIs"), removes
the cap for lpi_id_bits, which causes the following warning to trigger on a
QDF2400 server:WARNING: CPU: 0 PID: 0 at mm/page_alloc.c:4066 __alloc_pages_nodemask
...
Call trace:
__alloc_pages_nodemask+0x2d8/0x1188
alloc_pages_current+0x8c/0xd8
its_allocate_prop_table+0x5c/0xb8
its_init+0x220/0x3c0
gic_init_bases+0x250/0x380
gic_acpi_init+0x16c/0x2a4In its_alloc_lpi_tables(), lpi_id_bits is 24 in QDF2400. The allocation in
allocate_prop_table() tries therefore to allocate 16M (order 12 if
pagesize=4k), which triggers the warning.As said by MarcL
Capping lpi_id_bits at 16 (which is what we had before) is plenty,
will save a some memory, and gives some margin before we need to push
it up again.Bring the upper limit of lpi_id_bits back to prevent
Fixes: fe8e93504ce8 ("irqchip/gic-v3-its: Use full range of LPIs")
Suggested-by: Marc Zyngier
Signed-off-by: Jia He
Signed-off-by: Thomas Gleixner
Acked-by: Marc Zyngier
Tested-by: Olof Johansson
Cc: Jason Cooper
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lkml.kernel.org/r/1535432006-2304-1-git-send-email-jia.he@hxt-semitech.com
27 Aug, 2018
1 commit
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Pull irq update from Thomas Gleixner:
"A small set of updats/fixes for the irq subsystem:- Allow GICv3 interrupts to be configured as wake-up sources to
enable wakeup from suspend- Make the error handling of the STM32 irqchip init function work
- A set of small cleanups and improvements"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
irqchip/gic-v3: Allow interrupt to be configured as wake-up sources
irqchip/tango: Set irq handler and data in one go
dt-bindings: irqchip: renesas-irqc: Document r8a774a1 support
irqchip/s3c24xx: Remove unneeded comparison of unsigned long to 0
irqchip/stm32: Fix init error handling
irqchip/bcm7038-l1: Hide cpu offline callback when building for !SMP
24 Aug, 2018
1 commit
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…arm-platforms into irq/urgent
Pull irqchip updates for 4.19, take #2 from Marc Zyngier:
- bcm7038: compilation fix for !SMP
- stm32: fix teardown on probe error
- s3c24xx: fix compilation warning
- renesas-irqc: r8a774a1 support
- tango: chained irq setup simplification
- gic-v3: allow wake-up sources
23 Aug, 2018
1 commit
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Pull Xtensa updates from Max Filippov:
- switch xtensa arch to the generic noncoherent direct mapping
operations- add support for DMA_ATTR_NO_KERNEL_MAPPING attribute
- clean up users of platform/hardware.h in generic Xtensa code
- fix assembly cache maintenance code for long cache lines
- rework noMMU cache attributes initialization
- add big-endian HiFi2 test_kc705_be CPU variant
* tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: add test_kc705_be variant
xtensa: clean up boot-elf/bootstrap.S
xtensa: make bootparam parsing optional
xtensa: drop variant IRQ support
xtensa: drop unneeded platform/hardware.h headers
xtensa: move PLATFORM_NR_IRQS to Kconfig
xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START
xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE
xtensa: rework noMMU cache attributes initialization
xtensa: increase ranges in ___invalidate_{i,d}cache_all
xtensa: limit offsets in __loop_cache_{all,page}
xtensa: platform-specific handling of coherent memory
xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute
xtensa: use generic dma_noncoherent_ops
22 Aug, 2018
2 commits
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Pull arch/h8300 updates from Yoshinori Sato.
* tag 'for-4.19' of git://git.sourceforge.jp/gitroot/uclinux-h8/linux:
h8300: fix IRQ no
arch/h8300: add a defconfig target
arch/h8300: eliminate kgbd.c warning
arch/h8300: eliminate ptrace.h warnings
h8300:let the checker know that size_t is ulong
h8300: Don't include linux/kernel.h in asm/atomic.h
h8300: remove unnecessary of_platform_populate call
h8300: Correct signature of test_bit()
h8300: irqchip: fix warning
h8300: switch to NO_BOOTMEM
h8300: gcc-8.1 fix
h8300: Add missing output register. -
Var "addr" type incorrect.
It have interrupt controler register address.
Type of void __iomem is correct.Signed-off-by: Yoshinori Sato
21 Aug, 2018
1 commit
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If an xtensa core provides an additional IRQ controller it should be
treated as a separate piece of hardware and be driven by an irqchip
driver.Signed-off-by: Max Filippov
20 Aug, 2018
3 commits
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Although GICv3 doesn't directly offers support for wake-up interrupts
and relies on external HW for this, it shouldn't prevent the driver
for such HW from doing it work.Let's set the required flags on the irq_chip structures.
Reported-by: Lina Iyer
Tested-by: Lina Iyer
Reviewed-by: Sudeep Holla
Signed-off-by: Marc Zyngier -
Replace the two separate calls for setting the irq handler and data with
a single irq_set_chained_handler_and_data() call.Signed-off-by: Martin Kaiser
Signed-off-by: Marc Zyngier -
…l/git/palmer/riscv-linux
Pull RISC-V updates from Palmer Dabbelt:
"This contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make
it to userspace. Support for three devices has been added:- the ISA-mandated timers on RISC-V systems.
- the ISA-mandated first-level interrupt controller on RISC-V
systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.- SiFive's platform-level interrupt controller, which talks to the
actual devices.In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:- build fixes for various configurations:
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary
for some 32-bit configurations.
* !SMP && PERF_EVENTS- Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.- Fixes to ptrace(), which while not being sufficient to fully make
GDB work are at least sufficient to get simple GDB tasks to work.- Early printk support via RISC-V's architecturally mandated SBI
console device.- A fix to our early debug trap handler to ensure it's always
aligned.These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.This tag boots a Fedora root filesystem on QEMU's master branch for
me, and before this morning's rebase (from 4.18-rc8 to 4.18) it booted
on the HiFive Unleashed.Thanks to Christoph Hellwig and the other guys at WD for getting the
new drivers in shape!"* tag 'riscv-for-linus-4.19-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
dt-bindings: interrupt-controller: RISC-V local interrupt controller
RISC-V: Fix !CONFIG_SMP compilation error
irqchip: add a SiFive PLIC driver
RISC-V: Add the directive for alignment of stvec's value
clocksource: new RISC-V SBI timer driver
RISC-V: implement low-level interrupt handling
RISC-V: add a definition for the SIE SEIE bit
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: simplify software interrupt / IPI code
RISC-V: remove timer leftovers
RISC-V: Add early printk support via the SBI console
RISC-V: Don't increment sepc after breakpoint.
RISC-V: implement __lshrti3.
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
13 Aug, 2018
4 commits
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Add a driver for the SiFive implementation of the RISC-V Platform Level
Interrupt Controller (PLIC). The PLIC connects global interrupt sources
to the local interrupt controller on each hart.This driver is based on the driver in the RISC-V tree from Palmer Dabbelt,
but has been almost entirely rewritten since, and includes many fixes
from Atish Patra.Signed-off-by: Christoph Hellwig
Acked-by: Thomas Gleixner
Reviewed-by: Atish Patra
[Binding update by Palmer]
Signed-off-by: Palmer Dabbelt -
irq_data->hwirq is unsigned long. This fixes GCC warning:
drivers/irqchip/irq-s3c24xx.c: In function 's3c_irqext0_type':
drivers/irqchip/irq-s3c24xx.c:253:19: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits]
if ((data->hwirq >= 0) && (data->hwirq
Signed-off-by: Marc Zyngier -
If there are any errors in stm32_exti_host_init() then it leads to a
NULL dereference in the callers. The function should clean up after
itself.Fixes: f9fc1745501e ("irqchip/stm32: Add host and driver data structures")
Reviewed-by: Ludovic Barre
Signed-off-by: Dan Carpenter
Signed-off-by: Marc Zyngier -
When compiling bmips with SMP disabled, the build fails with:
drivers/irqchip/irq-bcm7038-l1.o: In function `bcm7038_l1_cpu_offline':
drivers/irqchip/irq-bcm7038-l1.c:242: undefined reference to `irq_set_affinity_locked'
make[5]: *** [vmlinux] Error 1Fix this by adding and setting bcm7038_l1_cpu_offline only when actually
compiling for SMP. It wouldn't have been used anyway, as it requires
CPU_HOTPLUG, which in turn requires SMP.Fixes: 34c535793bcb ("irqchip/bcm7038-l1: Implement irq_cpu_offline() callback")
Signed-off-by: Jonas Gorski
Signed-off-by: Marc Zyngier
