13 Aug, 2017
1 commit
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We are planning to share more code between different NAND based
devices (SPI NAND, OneNAND and raw NANDs), but before doing that
we need to move the existing include/linux/mtd/nand.h file into
include/linux/mtd/rawnand.h so we can later create a nand.h header
containing all common structure and function prototypes.Signed-off-by: Boris Brezillon
Signed-off-by: Peter Pan
Acked-by: Vladimir Zapolskiy
Acked-by: Alexander Sverdlin
Acked-by: Wenyou Yang
Acked-by: Krzysztof Kozlowski
Acked-by: Han Xu
Acked-by: H Hartley Sweeten
Acked-by: Shawn Guo
Acked-by: Gregory CLEMENT
Acked-by: Neil Armstrong
Acked-by: Masahiro Yamada
Acked-By: Harvey Hunt
Acked-by: Tony Lindgren
Acked-by: Krzysztof Halasa
25 Jun, 2017
2 commits
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Currently, we use the fixed ACC timing 0x10804211. This is not the best
setting for each case. Actually, MTK NAND controller can adapt ACC timings
dynamically according to nfi clock frequence.
Implement the ->setup_data_interface() hook to optimize driver performance.Signed-off-by: Xiaolei Li
Signed-off-by: Boris Brezillon -
chip->select_chip will do nfc runtime configuration. There is no need to
do mtk_nfc_hw_init before it.Signed-off-by: Xiaolei Li
Signed-off-by: Boris Brezillon
01 Jun, 2017
3 commits
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MT2712 NAND FLASH Controller is similar to MT2701 except those following:
(1) MT2712 supports up to 148B spare size per 1KB size sector (the same
with 74B spare size per 512B size sector). There are three new spare
format: 61, 67, 74.
(2) MT2712 supports up to 80 bit ecc strength. There are three new ecc
strength level: 68, 72, 80.
(3) MT2712 ECC encode parity data register's start offset is 0x300, and
different with 0x10 of MT2701.
(4) MT2712 improves ecc irq function. When ECC works in ECC_NFI_MODE,
MT2701 will generate ecc irq number the same with ecc steps during
page read. However, MT2712 can only generate one ecc irq.Changes of this patch are:
(1) add two new variables named pg_irq_sel, encode_parity_reg0 in struct
mtk_ecc_caps.
(2) add new bitfield ECC_PG_IRQ_SEL for register ECC_IRQ_REG.
(3) add ecc strength array of mt2712.
(4) add spare size array of mt2712.
(5) add mt2712 nfc and ecc device compatiable and data.Signed-off-by: Xiaolei Li
Signed-off-by: Boris Brezillon -
ECC strength and spare size supported may be different among MTK NAND
FLASH Controller IPs.This patch contains changes as following:
(1) add new struct mtk_nfc_caps to support different spare size.
(2) add new struct mtk_ecc_caps to support different ecc strength.
(3) remove ECC_CNFG_xBIT define, use a for loop to do ecc strength config.
(4) remove PAGEFMT_SPARE_ define, use a for loop to do spare format config.
(5) malloc ecc->eccdata buffer according to max ecc strength of this IP.Signed-off-by: Xiaolei Li
Signed-off-by: Boris Brezillon -
The register NFI_PAGEFMT is always 32 bits length, so it is better to
do register program using writel() compare with writew().Signed-off-by: Xiaolei Li
Signed-off-by: Boris Brezillon
30 Jan, 2017
1 commit
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There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.Signed-off-by: Wei Yongjun
Acked-by: Marek Vasut
Signed-off-by: Boris Brezillon
07 Nov, 2016
1 commit
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The nand_scan_ident/tail() returns an appropriate error value when
it fails. Use it instead of the fixed error code -ENODEV.Signed-off-by: Masahiro Yamada
Reviewed-by: Marek Vasut
Signed-off-by: Boris Brezillon
19 Sep, 2016
1 commit
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When mtk_nfc_do_write_page() comparing the sector number,because the
sector number field is at the 12th-bit position of NFI_BYTELEN
register,the masked register should be shifted 12 bits before being
compared.The result of this bug may cause the second subpage has
incomplete ECC parity bytes.Signed-off-by: RogerCC Lin
Fixes: 1d6b1e464950 ("mtd: mediatek: driver for MTK Smart Device")
Signed-off-by: Boris Brezillon
11 Jul, 2016
1 commit
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Add support for mediatek's SDG1 NFC nand controller embedded in SoC
2701Signed-off-by: Jorge Ramirez-Ortiz
Signed-off-by: Boris Brezillon
Tested-by: Xiaolei Li
