12 May, 2007

3 commits

  • Russell King
     
  • Enable devices to signal interrupts via PCI memory cycles.

    rev6:
    * fix enable/disable typo, Michael Ellerman

    rev5:
    * fix up ack, enable, and disable for iop13xx_msi_chip

    rev4:
    * move smp compile fix to separate patch
    * use dynamic_irq_init in create_irq()
    * hookup mask/unmask routines in iop13xx_msi_chip

    rev3:
    * change msi.c to use linux/smp.h instead of asm/smp.h
    * call dynamic_irq_cleanup at destroy_irq time

    rev2:
    * destroy_irq did not take the full 128 bits of msi_irq_in_use into account
    * added missing '&' for calls to test_and_set_bit and clear_bit

    [ebiederm@xmission.com: review comments/suggestions]
    [dan.j.williams@intel.com: cleanups/forward port to 2.6-git]
    Signed-off-by: Daniel Wolstenholme
    Signed-off-by: Dan Williams
    Acked-by: Eric W. Biederman
    Signed-off-by: Andrew Morton
    Signed-off-by: Russell King

    Daniel Wolstenholme
     
  • arch/arm/plat-iop/io.c:26: error: conflicting types for '__iop3xx_ioremap'

    Signed-off-by: Russell King

    Russell King
     

07 May, 2007

1 commit


05 May, 2007

1 commit


03 May, 2007

1 commit


30 Apr, 2007

2 commits


17 Feb, 2007

3 commits


31 Dec, 2006

1 commit

  • Since iop13xx defines the PCI I/O spaces with physical resource addresses
    the __io macro needs to perform the physical to virtual conversion. I
    incorrectly assumed that this would be handled by ioremap, but drivers
    (like e1000) directly dereference the address returned from __io.

    Signed-off-by: Dan Williams
    Signed-off-by: Russell King

    Dan Williams
     

18 Dec, 2006

1 commit


08 Dec, 2006

1 commit

  • The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
    Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
    controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
    PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
    a system-on-a-chip RAID subsystem engine.

    The iop342 processor replaces the SAS controller with a second Xscale core
    for dual core embedded applications.

    The iop341 processor is the single core version of iop342.

    This patch supports the two Intel customer reference platforms iq81340mc
    for external storage and iq81340sc for direct attach (HBA) development.

    The developer's manual is available here:
    ftp://download.intel.com/design/iio/docs/31503701.pdf

    Changelog:
    * removed virtual addresses from resource definitions
    * cleaned up some unnecessary #include's

    Signed-off-by: Dan Williams
    Signed-off-by: Russell King

    Dan Williams