23 Oct, 2019
1 commit
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scfw think 'new_pretimeout' as the time stamp from now, not
the time before watchdog timeout which is different with kernel
define. Convert it to scfw's format.Signed-off-by: Robin Gong
Reviewed-by: Anson Huang
(cherry picked from commit 674332ac12ddf593d89e87517573b31be2bbead3)
21 Oct, 2019
1 commit
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When we do set-par for background framebuffer without on-the-fly
flag being set, we should also unset the enabled overlay framebuffer's
on-the-fly flag, otherwise the overlay framebuffer cannot be enabled
again properly because a full mode set procedure is needed for overlay
framebuffer as it experiences a period of time when background
framebuffer stops fetching frames.Signed-off-by: Liu Ying
(cherry picked from commit fad9437d99ae234f1c66087d47ad8a547f5f1142)
19 Oct, 2019
1 commit
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set minimal scaling factor with 20 for 8MM and 6SX GPU
Signed-off-by: Xianzhong
(cherry picked from commit 03f411ed00d173b683ff2d00edf6196724cccf9d)
12 Oct, 2019
6 commits
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Enable all SECO MUs and increase number of users on the first one.
Signed-off-by: Stéphane Dion
(cherry picked from commit 56099536022e7e66cfc932069aa4a4701d84aa0b) -
enable all SECO MUs and increase number of users on the first one.
Signed-off-by: Stéphane Dion
(cherry picked from commit 2197e1f3a75fe9d9832cff3aa979aa4235a1e7a7) -
Enabling use of the first SECO MU on i.MX8QM
Signed-off-by: Stephane Dion
(cherry picked from commit 2b65b323254965b1d563e0aee80e18678d631b9d) -
Enabling use of the first SECO MU on i.MX8QXP
Signed-off-by: Stephane Dion
(cherry picked from commit b7865b23439de010187a211d1c283d6159807569) -
Driver to communicate with SECO over messaging unit.
Expose a char device to user-space so user can write messages that
will be sent to SECO and read messages received from it.
Data that should be exchanged with SECO through shared memory are
indicated to this driver through ioctl calls.Signed-off-by: Stephane Dion
(cherry picked from commit eb721810fdc309b6a32a7a64c7686eaa6052cdc7) -
Documentation of device-tree entry describing messaging
unit (MU) used to communicate with SECO core on i.MX8.Signed-off-by: Stephane Dion
(cherry picked from commit 238c7e4dab3b500c61b7def62dcd940b9c103658)
11 Oct, 2019
1 commit
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Fix Coverity high impact and Vulkan 1.1.3 issues
Signed-off-by: Xianzhong
(cherry picked from commit b1c86d22ff27aefbd3d07b78d27cf5d7491cbc1c)
08 Oct, 2019
1 commit
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hsync in struct of drm_display_mode is modes's hsync rate in kHz.
But DP register should been set the value of Horizontal Sync Width
that is not define in DRM_MODE().
It could get by (mode->hsync_end - mode->hsync_start).Signed-off-by: Sandor Yu
27 Sep, 2019
1 commit
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- Refine the tx/rx impedance ratio setting.
- Set the RxWaterMark to fix the GEN3 link unstable issue on iMX8QM.Signed-off-by: Richard Zhu
(cherry picked from commit 13234ea070f3b0048c98b59200bb3ed85659d013)
26 Sep, 2019
4 commits
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If CRTC is active, we should send vblank event in vblank
interrupt handler to make sure it's sent precisely. This
patch caches the event to be sent at dpu_crtc->event in
the ->atomic_enable() and the ->atomic_flush() callbacks
and finally sends it out in dpu_vbl_irq_handler(). Since
we rely on the interrupt handler to send the event, we
call drm_crtc_vblank_get() to get a vblank refcount to
guarantee the interrupt is enabled when caching the event
in dpu_crtc_queue_state_event() and call drm_crtc_vblank_put()
to drop a vblank refcount in the interrupt handler.Signed-off-by: Liu Ying
(cherry picked from commit c5f325790615eb16fe5a448e4b0afa122a33c23e) -
The DRM atomic core ensures crtc->state->event is not NULL when
calling the ->atomic_disable() or the ->atomic_flush() callbacks.
So, let's remove the unnecessary NULL check warning on it.Signed-off-by: Liu Ying
(cherry picked from commit 834bff532fe22a79708459ec976da0a74a2e97e2) -
When a full modeset is needed, the CRTC could be totally disabled or
enabled/re-enabled after the modeset. If it's re-enabled, a vblank
event would be sent during the CRTC enablement procedure. So, a bogus
event should be killed in the ->atomic_disable() callback.Signed-off-by: Liu Ying
(cherry picked from commit cee2d80af5e38fb022973c023f548ff02a515882) -
The Kdoc for the event entry of struct drm_crtc_state mentions that the
simplest way to send vblank event when a CRTC is being disabled is that
calling drm_crtc_send_vblank_event() somewhen after drm_crtc_vblank_off()
has been called. This patch takes the way mentioned above to send vblank
event in the ->atomic_disable() callback.Signed-off-by: Liu Ying
(cherry picked from commit 5b1a8127d98daf13d9f9891dfad2589f339b63d5)
23 Sep, 2019
3 commits
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It is suitable for imx8qm and imx8qxp currently
Acked-by: Jun Li
Signed-off-by: Peter Chen
(cherry picked from commit c5068a42ef39fd97b46813fa51de00147826aaac) -
HDCP function could work in other TVs
but it failed with Sony TV when run hdcp enable/disable stress test.
The TMDS clock is not detected by Sony TV.
The TV seems time sensitive for HDMI TMDS.
Add 20ms delay before TMDS enable make it work.Signed-off-by: Sandor Yu
-
Signed-off-by: Julien Olivain
Reviewed-by: Zhou Peng
(cherry picked from commit d5ee37f96629716042bb0b8317ff8ea0000a769c)
21 Sep, 2019
1 commit
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As DPU fetchunits support ITU601(limited range)/ITU601_FR(full range)
and ITU709(limited range) YUV to RGB color space conversions, we may
add color encoding and color range properties support for planes.
Considering software backward compatibility, the default color encoding
is set to ITU601 with full color range.Signed-off-by: Liu Ying
(cherry picked from commit f491e24e65cb360fb0b3ce56f74d04fd80da77ab)
20 Sep, 2019
7 commits
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This patch adds mulitple pixel blend modes for DPU plane.
The modes are "None", "Pre-multiplied" and "Coverage".Signed-off-by: Liu Ying
(cherry picked from commit 1259fedbcf2a54f58b47e8531a09b35cc60a43f7) -
Now that we've already got proper default blend mode support,
we may introduce alpha in pixel feature for overlay planes.Signed-off-by: Liu Ying
(cherry picked from commit 4881b188f809d1e3de8662dff94b1b2dfc00a62a) -
DPU has no limitations on the plane's zpos, so we don't
have to limit the primary plane zpos to be zero and the
overlay plane zpos to be non-zero.Signed-off-by: Liu Ying
(cherry picked from commit 4487aca4ab19623e1995322871e6f14d48bfef74) -
This patch improves bailout path of dpu_plane_init().
As we'll add more drm properties to the planes later,
this would simply the code.Signed-off-by: Liu Ying
(cherry picked from commit 1a6ab9246b5d6e71e8a4a0a0b5ea15d7af0c9879) -
Without the new blend modes("None", "Pre-multiplied" and "Coverage")
introduced in the below commit, the old userspace assumes alpha in
pixel is per-premultiplied by default. So, let's support the default
blend mode properly.commit 468dba6432ca ("drm: Add per-plane pixel blend mode property")
Signed-off-by: Liu Ying
(cherry picked from commit ebb7b4874493a8fb42de636e9421877a54399177) -
Pixel blend modes represent the alpha blending equation
selection, describing how the pixels from the current
plane are composited with the background.Adds a pixel_blend_mode to drm_plane_state and a
blend_mode_property to drm_plane, and related support
functions.Defines three blend modes in drm_blend.h.
Changes since v1:
- Moves the blending equation into the DOC comment
- Refines the comments of drm_plane_create_blend_mode_property to not
enumerate the #defines, but instead the string values
- Uses fg.* instead of pixel.* and plane_alpha instead of plane.alpha
Changes since v2:
- Refines the comments of drm_plane_create_blend_mode_property:
1) Puts the descriptions (after the ":") on a new line
2) Adds explaining why @supported_modes need PREMUL as default
Changes since v3:
- Refines drm_plane_create_blend_mode_property(). drm_property_add_enum()
can calculate the index itself just fine, so no point in having the
caller pass it in.
- Since the current DRM assumption is that alpha is premultiplied
as default, define DRM_MODE_BLEND_PREMULTI as 0 will be better.
- Refines some comments.
Changes since v4:
- Adds comments in drm_blend.h.
- Removes setting default value in drm_plane_create_blend_mode_property()
as it is already in __drm_atomic_helper_plane_reset().
- Fixes to use state->pixel_blend_mode instead of using
plane->state->pixel_blend_mode in reset function.
- Rebases on drm-misc-next.Reviewed-by: Liviu Dudau
Signed-off-by: Lowry Li
Signed-off-by: Ayan Kumar Halder
Reviewed-by: Sean Paul
Link: https://patchwork.freedesktop.org/patch/245734/
(cherry picked from commit a5ec8332d4280500544e316f76c04a7adc02ce03)
(cherry picked from commit 468dba6432ca97eedc2b8d6e6cc8905cd1e1f34e) -
There are a lot of drivers that subclass drm_plane_state, all of them
duplicate the code that links together the plane with plane_state.On top of that, drivers that enable core properties also have to
duplicate the code for initializing the properties to their default
values, which in all cases are the same as the defaults from core.Change since v1:
- Make it consistent with the other helpers and require that both
plane and state not be NULL, suggested by Boris Brezillon and
Philipp Zabel.Reviewed-by: Laurent Pinchart
Signed-off-by: Alexandru Gheorghe
Reviewed-by: Philipp Zabel
Link: https://patchwork.freedesktop.org/patch/msgid/20180804161530.12275-2-alexandru-cosmin.gheorghe@arm.com
(cherry picked from commit 7f4de521001f4ea705d505c9f91f58d0f56a0e6d)
(cherry picked from commit f09b192bf1316f0e65fa2dbb5ba4c82a558867ae)
17 Sep, 2019
1 commit
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Problems:
- GPU hang when run Google Earth apk on 8MM EVK board
- Android DEQP/SKQP CTS have random failures
- Khronos ES20 CTS have random failuresAnalysis:
GPU got stuck in shader module when process specific data format,
this is caused by VSI GCNanoUltra Errata(HBN1286), which does not set
the specific intermediate register to 0 in hardware reset sequence after power up,
this wrong register will cause the unexpected result when process specific data type,
wrong behavior will happen and may cause out of bound access in shader programming.Fix:
GPU driver will submit the predefined command(dummy draw) with fake stream and shader,
also set scissor with (0,0,0,0) to avoid draw out, no pixel output on hardware pipeline,
this workaround can set the specific register to 0 as the effective SW remedy.Impact:
No obvious functionality and performance impact with dummy draw workaround,
it only takes several cycles in command fetch --> vertex shader --> primitive,
and then cull out of reset of GPU pipelines.This patch can fix the same GPU problem for 7ULP.
Signed-off-by: Xianzhong
(cherry picked from commit b14813c419b1f733c0945e99fc403b7a25774d24)
16 Sep, 2019
2 commits
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The CRTC background should be full screen instead of partial
screen, because the DRM core is likely to add configurable
background color support in the future. We may cover the full
screen with ConstFrame0/1, upon which builds planes. With this,
it is easier to compute each plane's layer offset vs CRTC start
point and all ConstFrame units can be controlled by CRTC.Signed-off-by: Liu Ying
(cherry picked from commit ba18a9874cf010032413ca70f9b358399a143037) -
By correcting plane's ExtDst source in ->atomic_begin() for
cases where pixel combiner is used, commit[1] acctually fixes
the primary plane on-the-fly disablement failure issue which
commit[2] tries to address. So, let's revert commit[2] and
allow primary plane on-the-fly disablement.[1] commit 2f3eaadf72c3 ("MLK-22584 drm/imx: dpu: crtc: Correct plane's ExtDst source in ->atomic_begin()")
[2] commit 6477bb1492b7 ("MLK-21525 drm/imx: dpu: kms: Disallow primary plane on-the-fly disablement")Revert "MLK-21525 drm/imx: dpu: kms: Disallow primary plane on-the-fly disablement"
This reverts commit 6477bb1492b7ac89678891447f3d794e4fdb6df6.
Signed-off-by: Liu Ying
(cherry picked from commit 148075a270dafa0a04f1c9b61d62e2764e469cf3)
12 Sep, 2019
6 commits
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Change DMA_BUF_IOCTL_PHYS NR to 10 avoid conflicts with upstream
in the future.Reviewed-by: Song Bing
Signed-off-by: Dong Aisheng
(cherry picked from commit 36abba8f55078424e037e7f7877e9f22062cccbc) -
change DRM_FORMAT_MOD_VENDOR_VSI to 0xf1 to avoid conflicts
with upstream in the future.Reviewed-by: Liu Ying
Signed-off-by: Dong Aisheng
(cherry picked from commit aa4bedcc4c316d8d9400c3709840d5622e64e9b8) -
change DRM_FORMAT_MOD_VENDOR_AMPHION to 0xf0 to avoid conflicts
with upstream in the future.Reviewed-by: Liu Ying
Signed-off-by: Dong Aisheng
(cherry picked from commit c91d6eb654f557f683e5cdd44181581adbe15378) -
In dpu_helper_funcs->atomic_begin(), we temporarily set the plane's
ExtDst source to ConstFrame in shadow. In the plane driver,
dpu_plane_helper_funcs->atomic_update() can update the shadow if
necessary. This way, we may set the source as either ConstFrame
or LayerBlend. We only set the source for the old top plane in
->atomic_begin(). However, in cases where pixel combiner is used,
the top planes are tracked separately for the master stream and
the slave stream with ->is_left_top or ->is_right_top flags
instead of ->is_top flag when pixel combiner is not used. This
patch corrects the source for the cases where pixel combiner is
used.Signed-off-by: Liu Ying
(cherry picked from commit ff19118af177bab2dc765b242cf5b4392910a5e7) -
The bit DIV0 of register STORE9_STATIC is used as a control bit
to fix the unsynchronization issue bewteen two display streams
in FrameGen side-by-side mode, which is introduced from an ECO
operation for the display controller. The bit has to be one
when the side-by-side mode is enabled. And, it has to be zero
when the mode is disabled, otherwise, a single display stream
cannot startup correctly. Since the DPU common driver initializes
the register for us at the driver probe stage and system resume
stage, we may remove the same initialization logic of our own.
Without this patch, as the DPU blit engine DRM driver is resumed
relatively late, the bit would be overwritten to be zero at the
driver's ->resume() callback, which causes the display controller
cannot be correctly resumed from FrameGen side-by-side mode and
content ExtDst shadow load done event from the slave stream won't
come.Signed-off-by: Liu Ying
(cherry picked from commit 785a8705624e114f4f3d3d0836826130fb57b46f) -
The bit DIV0 of register STORE9_STATIC is used as a control bit
to fix the unsynchronization issue bewteen two display streams
in FrameGen side-by-side mode, which is introduced from an ECO
operation for the display controller. The bit has to be one
when the side-by-side mode is enabled. And, it has to be zero
when the mode is disabled, otherwise, a single display stream
cannot startup correctly. As Store9 is a part of blit engine,
the rest bits of the register should also be initialized before
any regular blit. Currently, we need to do the initialization
at driver probe stage and system resume stage at least. Since
we have the DPU KMS driver and DPU blit engine DRM driver, the
initialization needs to be done only in the DPU common driver
so that the register won't be overwritten accidentally by the
two drivers with each other. We see the overwriting issue at
the system resume stage because the blit engine driver resumes
relatively late and it initializes the register blindly by
writing the bit to zero, thus the display controller cannot be
resumed correctly in FrameGen side-by-side mode and content
ExtDst shadow load done event from the slave stream won't come.Signed-off-by: Liu Ying
(cherry picked from commit e90a6a917e3f5d7087e0de5616b6e8a055906767)
11 Sep, 2019
2 commits
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if stream status is on,
reqbufs will fail,
return -EBUSY instead of -EINVALSigned-off-by: ming_qian
(cherry picked from commit 65cfc81f73639c633d9e9b7c23c9c58443fa661f) -
driver tell seek and res change by the status of output stream.
if res change is not handled properly,
the stream may hang.Signed-off-by: ming_qian
Reviewed-by: Shijie Qin
(cherry picked from commit 86163d3eab3760f9659c7a58ff4cdf1a0a58a810)
10 Sep, 2019
2 commits
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If the port receives the resume during the suspending, it needs to
quit instead of going on, it could keep controller status correct,
and eliminating below timeout warning message.cdns-usb3 5b110000.usb3: wait lpm_clk_req timeout
cdns-usb3 5b110000.usb3: wait phy_refclk_req timeoutReviewed-by: Jun Li
Signed-off-by: Peter Chen -
If the non-control endpoints want to halt, but there are pending
requests on this endpoint, we need to return -EAGAIN, otherwise,
the controller may be in stuck if we stall the doolbell'ed
endpoint.With this change, we could pass the USB certification MSC test.
Reviewed-by: Jun Li
Signed-off-by: Peter Chen