23 Mar, 2016
1 commit
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This config is selected by CONFIG_ARCH_HISI, so there is no point to have it
user configurable.While at it move the config option to the proper place in the alphabetically
sorted option list.Requested-by: Thomas Gleixner
Signed-off-by: Ma Jun
Cc: mark.rutland@arm.com
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: Catalin.Marinas@arm.com
Cc: guohanjun@huawei.com
Cc: Will.Deacon@arm.com
Cc: huxinwei@huawei.com
Cc: lizefan@huawei.com
Cc: dingtianhong@huawei.com
Cc: zhaojunhua@hisilicon.com
Cc: liguozhu@hisilicon.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1458723993-21044-3-git-send-email-majun258@huawei.com
Signed-off-by: Thomas Gleixner
21 Mar, 2016
2 commits
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Each mbigen device is represented as a independent platform device. If the
devices belong to the same mbigen hardware module, then the register space for
these devices is the same. That leads to a resource conflict.The solution for this is to represent the mbigen module as a platform device
and make the mbigen devices subdevices of that. The register space is
associated to the mbigen module and therefor the resource conflict is avoided.[ tglx: Massaged changelog, cleaned up the code and removed the silly printk ]
Signed-off-by: Ma Jun
Cc: mark.rutland@arm.com
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: Catalin.Marinas@arm.com
Cc: guohanjun@huawei.com
Cc: Will.Deacon@arm.com
Cc: huxinwei@huawei.com
Cc: lizefan@huawei.com
Cc: dingtianhong@huawei.com
Cc: zhaojunhua@hisilicon.com
Cc: liguozhu@hisilicon.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1458203641-17172-3-git-send-email-majun258@huawei.com
Signed-off-by: Thomas Gleixner -
Current code calls irq_domain_alloc_irqs_parent() in .alloc,
so it should call irq_domain_free_irqs_parent() accordingly in .free.
Fix it by switching to use irq_domain_free_irqs_common() instead of
the open-coded private implementation.Signed-off-by: Axel Lin
Cc: Alexandre Courbot
Cc: Jason Cooper
Cc: Stephen Warren
Cc: Marc Zyngier
Cc: Thierry Reding
Cc: linux-tegra@vger.kernel.org
Link: http://lkml.kernel.org/r/1458477845.28679.1.camel@ingics.com
Signed-off-by: Thomas Gleixner
11 Mar, 2016
1 commit
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The "msi_domain" variable is NULL here so it leads to a NULL dereference. It
looks like we actually intended to free "middle_domain".Fixes: e6b78f2c3e14 ('irqchip: Add the Alpine MSIX interrupt controller')
Signed-off-by: Dan Carpenter
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Antoine Tenart
Cc: kernel-janitors@vger.kernel.org
Cc: Tsahee Zidenberg
Link: http://lkml.kernel.org/r/20160311081442.GE31887@mwanda
Signed-off-by: Thomas Gleixner
10 Mar, 2016
2 commits
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The of_io_request_and_map() returns a valid pointer in iomem region or
ERR_PTR(), check for NULL always fails and may cause a NULL pointer
dereference on error path.Fixes: 25e34b44313b ("irqchip/mxs: Prepare driver for hardware with different offsets")
Signed-off-by: Vladimir Zapolskiy
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Oleksij Rempel
Cc: Sascha Hauer
Cc: Shawn Guo
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1457486500-10237-1-git-send-email-vz@mleia.com
Signed-off-by: Thomas Gleixner -
The of_io_request_and_map() returns a valid pointer in iomem region or
ERR_PTR(), check for NULL always fails and may cause a NULL pointer
dereference on error path.Fixes: 0e841b04c829 ("irqchip/sunxi-nmi: Switch to of_io_request_and_map() from of_iomap()")
Signed-off-by: Vladimir Zapolskiy
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Chen-Yu Tsai
Cc: Maxime Ripard
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1457486489-10189-1-git-send-email-vz@mleia.com
Signed-off-by: Thomas Gleixner
09 Mar, 2016
8 commits
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In the add-on file for the GIC dealing with the RealView family
we currently only handle the PB11MPCore, let's extend this to
manage the RealView EB ARM11MPCore as well. The Revision B of the
ARM11MPCore core tile is a bit special and needs special handling
as it moves a system control register around at random.Cc: Arnd Bergmann
Cc: devicetree@vger.kernel.org
Acked-by: Marc Zyngier
Signed-off-by: Linus Walleij
Signed-off-by: Marc Zyngier -
This patch adds the Alpine MSIX interrupt controller driver.
Signed-off-by: Antoine Tenart
Signed-off-by: Tsahee Zidenberg
Acked-by: Marc Zyngier
Signed-off-by: Marc Zyngier -
Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the
affinity has been updated. When using stacked irqchips, returning
IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips.Signed-off-by: Antoine Tenart
Acked-by: Marc Zyngier
Signed-off-by: Marc Zyngier -
gicv3_init_bases() is the only caller for its_init(),
also it is a __init function, so mark its_init() as __init too,
then recursively mark the functions called as __init.This will help to introduce ITS initialization using ACPI tables as
we will use acpi_table_parse_entries family functions there which
belong to __init section as well.Acked-by: Marc Zyngier
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
Signed-off-by: Marc Zyngier -
The gic_root_node variable defined in ITS driver is not actually
used, so just remove it.Acked-by: Marc Zyngier
Signed-off-by: Hanjun Guo
Signed-off-by: Marc Zyngier -
Following ACPI spec:
On systems supporting GICv3 and above, GICR Base Address in MADT GICC
structure holds the 64-bit physical address of the associated Redistributor.
If all of the GIC Redistributors are in the always-on power domain,
GICR structures should be used to describe the Redistributors instead,
and this field must be set to 0.It means that we have two ways to initialize registirbutors map.
1. via GICD structure which can accommodate many redistributors as a region
2. via GICC which is able to describe single redistributorThis patch is going to add support for second option.
Considering redistributors, GICD and GICC subtables have be mutually
exclusive. While discovering and mapping redistributor, we need to know
its size in advance. For the GICC case, redistributor can be in
a power-domain that is off, thus we cannot relay on GICR TYPER register.
Therefore, we get GIC version from distributor register and map 2xSZ_64K
for GICv3 and 4xSZ_64K for GICv4.Acked-by: Marc Zyngier
Signed-off-by: Hanjun Guo
Signed-off-by: Tomasz Nowicki
Signed-off-by: Marc Zyngier -
With the refator of gic_of_init(), GICv3/4 can be initialized
by gic_init_bases() with gic distributor base address and gic
redistributor region(s).So get the redistributor region base addresses from MADT GIC
redistributor subtable, and the distributor base address from
GICD subtable to init GICv3 irqchip in ACPI way.Note: GIC redistributor base address may also be provided in
GICC structures on systems supporting GICv3 and above if the GIC
Redistributors are not in the always-on power domain, this
patch didn't implement such feature yet.Acked-by: Marc Zyngier
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
Signed-off-by: Marc Zyngier -
Isolate hardware abstraction (FDT) code to gic_of_init().
Rest of the logic goes to gic_init_bases() and expects well
defined data to initialize GIC properly. The same solution
is used for GICv2 driver.This is needed for ACPI initialization later.
Acked-by: Marc Zyngier
Signed-off-by: Tomasz Nowicki
Signed-off-by: Hanjun Guo
Signed-off-by: Marc Zyngier
08 Mar, 2016
1 commit
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Signed-off-by: Ingo Molnar
25 Feb, 2016
6 commits
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The new property will allow to specify the range of GIC hwirqs to use for IPIs.
This is an optinal property. We preserve the previous behaviour of allocating
the last 2 * gic_vpes if it's not specified or DT is not supported.Signed-off-by: Qais Yousef
Acked-by: Rob Herring
Acked-by: Ralf Baechle
Cc:
Cc:
Cc:
Cc:
Cc:
Cc: Qais Yousef
Link: http://lkml.kernel.org/r/1449580830-23652-20-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner -
This commit does several things to avoid breaking bisectability.
1- Remove IPI init code from irqchip/mips-gic
2- Implement the new irqchip->send_ipi() in irqchip/mips-gic
3- Select GENERIC_IRQ_IPI Kconfig symbol for MIPS_GIC
4- Change MIPS SMP to use the generic IPI implementationOnly the SMP variants that use GIC were converted as it's the only irqchip that
will have the support for generic IPI for now.Signed-off-by: Qais Yousef
Acked-by: Ralf Baechle
Cc:
Cc:
Cc:
Cc:
Cc:
Cc: Qais Yousef
Link: http://lkml.kernel.org/r/1449580830-23652-18-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner -
When setting the mapping for a hwirq, make sure we clear percpu_masks for
all other cpus in case it was set previously.Signed-off-by: Qais Yousef
Acked-by: Ralf Baechle
Cc:
Cc:
Cc:
Cc:
Cc:
Cc: Qais Yousef
Link: http://lkml.kernel.org/r/1449580830-23652-16-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner -
NR_CPUS is set by Kconfig and could be much higher than what actually is in the
system.gic_vpes should be a true representitives of the number of cpus in the system,
so use it instead.Signed-off-by: Qais Yousef
Acked-by: Ralf Baechle
Cc:
Cc:
Cc:
Cc:
Cc:
Cc: Qais Yousef
Link: http://lkml.kernel.org/r/1449580830-23652-15-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner -
Now the root gic_irq_domain is split into device and IPI domains.
This form provides a better representation of how the root domain is split into
2. One for devices and one for IPIs.Signed-off-by: Qais Yousef
Acked-by: Ralf Baechle
Cc:
Cc:
Cc:
Cc:
Cc:
Cc: Qais Yousef
Link: http://lkml.kernel.org/r/1449580830-23652-14-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner -
Add a new ipi domain on top of the normal domain.
MIPS GIC now supports dynamic allocation of an IPI.
Signed-off-by: Qais Yousef
Acked-by: Ralf Baechle
Cc:
Cc:
Cc:
Cc:
Cc:
Cc: Qais Yousef
Link: http://lkml.kernel.org/r/1449580830-23652-13-git-send-email-qais.yousef@imgtec.com
Signed-off-by: Thomas Gleixner
22 Feb, 2016
2 commits
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Pull the second round of irqchip core changes for v4.6 from Jason Cooper:
- mvebu:
- Add odmi driver for Marvell 7K/8K SoCs
- Replace driver-specific set_affinity with generic version- mips:
- Move ath79 MISC and CPU drivers from arch/ code to irqchip/- tango:
- Add support for Sigma Designs SMP8[67]xx ctrl -
Pull irqchip core changes for v4.6 from Jason Cooper:
- mvebu (armada-370-xp)
- MSI support
- Deconflict with mvebu's arm64 code- ts4800
- Restrict when ts4800 driver can be built
- Make ts4800_ic_ops static const- bcm2836: Drop superfluous memory barrier
21 Feb, 2016
3 commits
19 Feb, 2016
2 commits
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Moving an SPI around doesn't require any extra work from the rest
of the stack, and specially not for MSI-generated SPIs.It is then worth returning IRQ_SET_MASK_OK_DONE instead of
IRQ_SET_MASK_OK, and simplify the other irqchips that rely on
this behaviour (GICv2m and Marvell's ODMI controller).Signed-off-by: Marc Zyngier
Acked-by: Thomas Petazzoni
Link: https://lkml.kernel.org/r/1455894029-17270-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper -
This commits adds a new irqchip driver that handles the ODMI
controller found on Marvell 7K/8K processors. The ODMI controller
provide MSI interrupt functionality to on-board peripherals, much like
the GIC-v2m.Signed-off-by: Thomas Petazzoni
Reviewed-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
18 Feb, 2016
5 commits
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ts4800_ic_ops is only referenced in this driver, so make it static.
In additional, it's never get modified thus also make it const.Signed-off-by: Axel Lin
Reviewed-by: Damien Riegel
Link: https://lkml.kernel.org/r/1455457804.13175.1.camel@ingics.com
Signed-off-by: Jason Cooper -
The writel() immediately after this has a barrier, anyway.
Signed-off-by: Eric Anholt
Link: https://lkml.kernel.org/r/1454620468-31303-1-git-send-email-eric@anholt.net
Signed-off-by: Jason Cooper -
The Technologic Systems TS-4800 is an i.MX515 board, so its drivers
are useless unless building a SOC_IMX51 kernel, except for build
testing purposes.Signed-off-by: Jean Delvare
Cc: Damien Riegel
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Link: https://lkml.kernel.org/r/20160209111920.1ec318bd@endymion
Signed-off-by: Jason Cooper -
This adds support for the secondary interrupt controller used in Sigma
Designs SMP86xx and SMP87xx chips.Signed-off-by: Mans Rullgard
Acked-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1453313237-18570-2-git-send-email-mans@mansr.com
Signed-off-by: Jason Cooper -
Function its_alloc_tables() maintains two local variables, "order" and
and "alloc_size", to hold memory size that has been allocated to
ITS_BASEn. We don't always refresh the variable alloc_size whenever
value of the variable order changes, causing the following two
problems.- Cache flush operation with size more than required.
- Information reported by pr_info is not correct.Use a helper macro that converts page order to size in bytes instead of
variable "alloc_size" to fix both the problems.Signed-off-by: Shanker Donthineni
Signed-off-by: Marc Zyngier
17 Feb, 2016
7 commits
-
Signed-off-by: Alban Bedel
Acked-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1453553867-27003-2-git-send-email-albeu@free.fr
Signed-off-by: Jason Cooper -
The driver stays the same but the initialization changes a bit.
For OF boards we now get the memory map from the OF node and use
a linear mapping instead of the legacy mapping. For legacy boards
we still use a legacy mapping and just pass down all the parameters
from the board init code.Signed-off-by: Alban Bedel
Acked-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.fr
Signed-off-by: Jason Cooper -
The irq-armada-370-xp driver can only be built for ARM 32 bits. The mvebu
family had grown with a new ARM64 SoC which will also select the
ARCH_MEVBU configuration. Since "ARM: mvebu: use the ARMADA_370_XP_IRQ
option", the ARM32 mvebu SoC directly select this new option. Selecting
it by default when ARCH_MEVBU is selected is no more needed.This patch removes this dependency, thanks to this, a kernel for ARM64
mvebu SoC can be built without error due this driver.Signed-off-by: Gregory CLEMENT
Link: https://lkml.kernel.org/r/1454951660-13289-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper -
Add support for allocating multiple MSIs at the same time, so that the
MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info
structure.Signed-off-by: Thomas Petazzoni
Reviewed-by: Gregory CLEMENT
Link: https://lkml.kernel.org/r/1455115621-22846-6-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
In order to make the output of /proc/interrupts, use shorter names for
the irq_chip registered by the irq-armada-370-xp driver. Using capital
letters also matches better what is done for the GIC driver, which
uses just "GIC" as the irq_chip->name.Signed-off-by: Thomas Petazzoni
Acked-by: Gregory CLEMENT
Link: https://lkml.kernel.org/r/1455115621-22846-5-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
As suggested by Gregory Clement, this commit adjusts the
irq-armada-370-xp driver to use the PCI_MSI_DOORBELL_START define in
the armada_370_xp_handle_msi_irq() function, rather than hardcoding
its value.Suggested-by: Gregory CLEMENT
Signed-off-by: Thomas Petazzoni
Acked-by: Gregory CLEMENT
Link: https://lkml.kernel.org/r/1455115621-22846-4-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper -
This commit moves the irq-armada-370-xp driver from using the
PCI-specific MSI infrastructure to the generic MSI infrastructure, to
which drivers are progressively converted.In this hardware, the MSI controller is directly bundled inside the
interrupt controller, so we have a single Device Tree node to which
multiple IRQ domaines are attached: the wired interrupt domain and the
MSI interrupt domain. In order to ensure that they can be
differentiated, we have to force the bus_token of the wired interrupt
domain to be DOMAIN_BUS_WIRED. The MSI domain bus_token is
automatically set to the appropriate value by
pci_msi_create_irq_domain().Signed-off-by: Thomas Petazzoni
Suggested-by: Marc Zyngier
Reviewed-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1455115621-22846-3-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper
