02 Nov, 2018
2 commits
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Add pio spi slave mode support for imx6ul which is based on the patch
cherry-pick from community(71abd29057cb17b6b9532421821dc443427399ed).Because the original imx6ul is bound to mx51 in the dts file.
However, in the slave mode, the patch in the community only adds two
functions mx53_ecspi_rx_slave/mx53_ecspi_tx_slave. Therefore, configure
mx51/6ul to use these two functions for data transmission and reception
in slave mode.Acked-by: Fugang Duan
Signed-off-by: Clark Wang -
Previously i.MX SPI controller only works in Master mode.
This patch adds support to i.MX51, i.MX53 and i.MX6 ECSPI
controller to work also in Slave mode.Currently SPI Slave mode support patch has the following limitations:
1. The stale data in RXFIFO will be dropped when the Slave does any new
transfer.
2. One transfer can be finished only after all transfer->len data been
transferred to master device
3. Slave device only accepts transfer->len data. Any data longer than this
from master device will be dropped. Any data shorter than this from
master will cause SPI to stuck due to mentioned HW limitation 2.
4. Only PIO transfer is supported in Slave mode.
5. Dynamic burst size adjust isn't supported in Slave mode.Following HW limitation applies:
1. ECSPI has a HW issue when works in Slave mode, after 64
words written to TXFIFO, even TXFIFO becomes empty,
ECSPI_TXDATA keeps shift out the last word data,
so we have to disable ECSPI when in slave mode after the
transfer completes
2. Due to Freescale errata ERR003775 "eCSPI: Burst completion by Chip
Select (SS) signal in Slave mode is not functional" burst size must
be set exactly to the size of the transfer. This limit SPI transaction
with maximum 2^12 bits. This errata affects i.MX53 and i.MX6 ECSPI
controllers.Signed-off-by: Jiada Wang
Signed-off-by: Mark Brown
29 Oct, 2018
24 commits
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Use SR_TDF to judge if need send data, and SR_FCF to judge if
transmission end to replace the waiting after transmission end. This
waiting has no actual meaning, for the real end will set the FCF
flag.Resolved an issue that could cause a transmission timeout when
transferring large amounts of data.After making these changes, there is no need to use
fsl_lpspi_txfifo_empty(), so remove it.Signed-off-by: Xiaoning Wang
Reviewed-by: Fugang Duan -
Remove Reset operation in fsl_lpspi_config(). This RST may cause both CLK and
CS pins go from high to low level under cs-gpio mode.
Add fsl_lpspi_reset() function after one message transfer to clear all
flags in use.Signed-off-by: Xiaoning Wang
Reviewed-by: Fugang Duan -
enable the runtime pm for lpspi module
BuildInfo:
- U-Boot 2018.03-imx_4.14.ySigned-off-by: Han Xu
Reviewed-by: Frank Li
Signed-off-by: Xiaoning Wang -
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards.
Signed-off-by: Xiaoning Wang
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Add new setup_wml() for i.mx6ul, otherwise, kernel crash triggered
since no such function on i.mx6ul.This issue is brought by
commit 85c124bbc1c4 ("MLK-18983-1: spi: imx: move wml setting to
later than setup_transfer").Signed-off-by: Robin Gong
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Correct wml as the last rx sg length instead of the whole transfer
length.Signed-off-by: Robin Gong
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Current dynamic burst lengt
h is based on the whole transfer length,
that's ok if there is only one sg, but not correct in case multi sgs
in one transfer,because the tail data should based on the last sg
length instead of the whole transfer length. Move wml setting for DMA
to the later place, thus, the next patch could get the right last sg
length for wml setting. This patch is a preparation one, no any
function change involved.Signed-off-by: Robin Gong
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Add SPI slave mode for imx7ulp.
Need use imx7ulp-evk-spi-slave.dtb to boot.
Slave has to send the message which is same as the length of message
master sent.Wire connection:
GND, SCK, MISO(to MISO of slave), MOSI(to MOSI of slave), SCSSigned-off-by: Xiaoning Wang
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fsl,spi-num-chipselects may not assigned in DT, don't return EINVALID in
this case.Signed-off-by: Han Xu
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Below description copied from RM:
"RX_THRESHOLD. This field defines the FIFO threshold that triggers
a RX DMA/INT request.A RX DMA/INT request is issued when the number
of data entries in the RXFIFO is greater than RX_THRESHOLD."
Then, the RX_THRESHOLD of ECSPIx_DMAREG should be set as 'wml-1',
otherwise, the last 'wml' number of data in rxfifo will never be pulled
out.Signed-off-by: Robin Gong
Reviewed-by: Han Xu -
Upstreaming code already support dynamically adjust watermark with
the transfer count, so in case 'wml=1', tx wml will be set to 0
after divided by 2, which cause tx dma never start.Actually, don't
need promise tx_wml=rx_wml/2 any more, because the max wml for tx/rx
is half of fifo size and sdma script have already check the data count
in RXFIFO, if more than half of rxfifo data remain in rxfifo, tx dma
will never start transfer next 'watermark'(the max count maybe the half
of fifo size) data until the data in rxfifo less than half of rxfifo.
So never any data loss happen. Remove 'wml/2'.Signed-off-by: Robin Gong
Reviewed-by: Han Xu -
This patch revert "MLK-17619: spi: ecspi: request gpio resources
before setting the value", because spi_imx_setup() will be called
several times accroding to the spc definition. So remove the gpio
request operation out from spi_imx_setup(), and back to probe(),
and move up the location, just incase set the cs gpio value before
request gpio resources.This reverts commit aba5f6342002ffe1f13a71dbddf30ec15ee1edba.
-
gpio controller ignored all values were set before request resources,
move the devm_gpio_request to spi_imx_setup to fix the issue.Signed-off-by: Han Xu
Suggested-and-reviewed-by: Fugang Duan -
The spi_imx IP block is also present on i.MX8M, so allow it
to be built for this platform.Signed-off-by: Fabio Estevam
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Use PIO if transfer length is smaller than wml instead of DMA mode.
That means some spi-nor driver such as m25p32 may setup one small size
transfer to probe device id from external spi-nor devicee by PIO mode
instead of DMA which can avoid checking sdma firmware ready during spi-nor
driver probe.Signed-off-by: Robin Gong
Acked-by: Fugang Duan -
1. Fix code error of changing lpspi clock polarity.
2. Set one SPI clock period for DBT parameter.
Signed-off-by: Gao Pan
Reviewed-by: Han Xu -
enable the lpspi config for arm64 in Kconfig
BuildInfo: SCFW 9e9f6ec6, IMX-MKIMAGE 0, ATF 0
Reviewed-by: Pan Gao
Signed-off-by: Han Xu -
Add imx6ul device type in spi driver to enable the ERR008517 workaround
or not by dts easily.Signed-off-by: Robin Gong
-
To workaroud the TKT238285, the safe way is use XCH mode in SDMA
script to simulate as PIO mode which never report such issue. Meanwhile,
set tx threashold as 0. But this workaroud will bring performance impacted,
below performance data is collected by 'dd' with SPI-NOR flash on i.mx6dl
sabresd board:mode write data read data
--PIO 194KB/s 644KB/s
--DMA normal
(SMC, tx_thresh=32) 222KB/s 1.4MB/s
--DMA(XCH, tx_thresh=0) 210KB/s 1.0MB/sSigned-off-by: Robin Gong
(cherry picked from commit 01be65fa5617aa192307ca38b6fc6128f3f0c3f7)
(cherry picked from commit 646a751a4d1d0e227a762b461d9b8f92605c26b1)
(cherry picked from commit b334993950b24ced30fcfc70c126b65bf4cb4cff)Conflicts:
drivers/spi/spi-imx.c -
On i.MX7ULP sillicon, system suspend go through VLLS mode that gate
off pinctrl and modules power, then all registers are reset to HW
default value. To support the feature, driver needs to recover all
registers status.Signed-off-by: Gao Pan
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SPI IOMUX is changed into reset state in LPSR mode. As a result,
spi can't work again.This patch sets spi IOMUX to default state.
(cherry-picked from commit 2c8603c31831bb355f6be5b015377fb8fbd89844)
Signed-off-by: Gao Pan
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This is done in preperation for low power mode. Convert all clk_enable
to clk_prepare_enable and clk_disable to clk_disable_unprepare. Make sure
PLL3 power down when entering low power mode.Signed-off-by: Bai Ping
(cherry picked from commit 1808b31fdae576e775159a05cde9b45e404bb6e2) -
There is official workaound for TKT238285, so remove the limitation
for i.mx6dl.Signed-off-by: Robin Gong
-
We set both wartermark of txfifo and rxfifo 32 as half of fifo length 64.
That will cause easy rxfifo overflow:
If there is 31 bytes in rxfifo, rx script will wait the next dma request
(the 32th data come into the rxfifo) and schedule out to tx script. Once
tx script start to run, the rx script need to wait tx script finish even
if its priority higher than tx. Meanwhile, spi slave device may input
data continous, plus the rx data which triggered by new tx script(32 bytes).
That will quickly consume whole 64 bytes fifo, so we keep 16bytes availbale
even in the worst case new tx script triggered during two rx transfer. That
may slow down tx slightly, but better than overflow and RX DMA timeout.Signed-off-by: Robin Gong
(cherry picked from commit 16043ad0ad96aa04a90614e473aa17980af4b8af)
(cherry picked from commit 819efee83b7b1f47685dca6fad6bbe17f1c42092)
(cherry picked from commit 5c4c7d05bbba0ea2b26ef2f3ae83119d5eada235)
04 Oct, 2018
5 commits
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commit 8dbbaa47b96f6ea5f09f922b4effff3c505cd8cf upstream.
When interrupted, wait_event_interruptible_timeout() returns
-ERESTARTSYS, and the SPI transfer in progress will fail, as expected:m25p80 spi0.0: SPI transfer failed: -512
spi_master spi0: failed to transfer one message from queueHowever, as the underlying DMA transfers may not have completed, all
subsequent SPI transfers may start to fail:spi_master spi0: receive timeout
qspi_transfer_out_in() returned -110
m25p80 spi0.0: SPI transfer failed: -110
spi_master spi0: failed to transfer one message from queueFix this by calling dmaengine_terminate_all() not only for timeouts, but
also for errors.This can be reproduced on r8a7991/koelsch, using "hd /dev/mtd0" followed
by CTRL-C.Signed-off-by: Geert Uytterhoeven
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman -
commit c1ca59c22c56930b377a665fdd1b43351887830b upstream.
If the SPI queue is running during system suspend, the system may lock
up.Fix this by stopping/restarting the queue during system suspend/resume,
by calling spi_master_suspend()/spi_master_resume() from the PM
callbacks. In-kernel users will receive an -ESHUTDOWN error while
system suspend/resume is in progress.Based on a patch for sh-msiof by Gaku Inami.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman -
commit 31a5fae4c5a009898da6d177901d5328051641ff upstream.
This patch changes writing to the SISTR register according to the H/W
user's manual.The TDREQ bit and RDREQ bits of SISTR are read-only, and must be written
their initial values of zero.Signed-off-by: Hiromitsu Yamasaki
[geert: reword]
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman -
commit ffa69d6a16f686efe45269342474e421f2aa58b2 upstream.
If the SPI queue is running during system suspend, the system may lock
up.Fix this by stopping/restarting the queue during system suspend/resume
by calling spi_master_suspend()/spi_master_resume() from the PM
callbacks. In-kernel users will receive an -ESHUTDOWN error while
system suspend/resume is in progress.Signed-off-by: Gaku Inami
Signed-off-by: Hiromitsu Yamasaki
[geert: Cleanup, reword]
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman -
commit 7001cab1dabc0b72b2b672ef58a90ab64f5e2343 upstream.
Depending on the SPI instance one may get an interrupt storm upon
requesting resp. interrupt unless the clock is explicitly enabled
beforehand. This has been observed trying to bring up instance 4 on
T20.Signed-off-by: Marcel Ziswiler
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman
29 Sep, 2018
2 commits
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commit 04b2d03a75652bda989de1595048f0501dc0c0a0 upstream.
If the SPI bus number is provided by a DT alias, idr_alloc() is called
twice, leading to:WARNING: CPU: 1 PID: 1 at drivers/spi/spi.c:2179 spi_register_controller+0x11c/0x5d8
couldn't get idrFix this by moving the handling of fixed SPI bus numbers up, before the
DT handling code fills in ctlr->bus_num.Fixes: 1a4327fbf4554d5b ("spi: fix IDR collision on systems with both fixed and dynamic SPI bus numbers")
Signed-off-by: Geert Uytterhoeven
Tested-by: Fabio Estevam
Signed-off-by: Mark Brown
Cc: Sudip Mukherjee
Cc: Kirill Kapranov
Signed-off-by: Greg Kroah-Hartman -
commit 1a4327fbf4554d5b78d75b19a13d40d6de220159 upstream.
On systems where some controllers get a dynamic ID assigned and some have
a fixed number (e.g. from ACPI tables), the current implementation might
run into an IDR collision: in case of a fixed bus number is gotten by a
driver (but not marked busy in IDR tree) and a driver with dynamic bus
number gets the same ID and predictably fails.Fix this by means of checking-in fixed IDsin IDR as far as dynamic ones
at the moment of the controller registration.Fixes: 9b61e302210e (spi: Pick spi bus number from Linux idr or spi alias)
Signed-off-by: Kirill Kapranov
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman
10 Sep, 2018
4 commits
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commit 931c4e9a72ae91d59c5332ffb6812911a749da8e upstream.
The path "spi: cadence: Add usleep_range() for
cdns_spi_fill_tx_fifo()" added a usleep_range() function call,
which cannot be used in atomic context.
However the cdns_spi_fill_tx_fifo() function can be called during
an interrupt which may result in a kernel panic:BUG: scheduling while atomic: grep/561/0x00010002
Modules linked in:
Preemption disabled at:
[] wait_for_common+0x48/0x178
CPU: 0 PID: 561 Comm: grep Not tainted 4.17.0 #1
Hardware name: Cadence CSP (DT)
Call trace:
dump_backtrace+0x0/0x198
show_stack+0x14/0x20
dump_stack+0x8c/0xac
__schedule_bug+0x6c/0xb8
__schedule+0x570/0x5d8
schedule+0x34/0x98
schedule_hrtimeout_range_clock+0x98/0x110
schedule_hrtimeout_range+0x10/0x18
usleep_range+0x64/0x98
cdns_spi_fill_tx_fifo+0x70/0xb0
cdns_spi_irq+0xd0/0xe0
__handle_irq_event_percpu+0x9c/0x128
handle_irq_event_percpu+0x34/0x88
handle_irq_event+0x48/0x78
handle_fasteoi_irq+0xbc/0x1b0
generic_handle_irq+0x24/0x38
__handle_domain_irq+0x84/0xf8
gic_handle_irq+0xc4/0x180This patch replaces the function call with udelay() which can be
used in an atomic context, like an interrupt.Signed-off-by: Jan Kotas
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman -
commit d8ffee2f551a627ffb7b216e2da322cb9a037f77 upstream.
Registers of DSPI should not be accessed before enabling its clock. On
Toradex Colibri VF50 on Iris carrier board this could be seen during
bootup as imprecise abort:Unhandled fault: imprecise external abort (0x1c06) at 0x00000000
Internal error: : 1c06 [#1] ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.14.39-dirty #97
Hardware name: Freescale Vybrid VF5xx/VF6xx (Device Tree)
Backtrace:
[] (regmap_write) from [] (dspi_probe+0x1f0/0x8dc)
[] (dspi_probe) from [] (platform_drv_probe+0x54/0xb8)
[] (platform_drv_probe) from [] (driver_probe_device+0x280/0x2f8)
[] (driver_probe_device) from [] (__driver_attach+0xc0/0xc4)
[] (__driver_attach) from [] (bus_for_each_dev+0x70/0xa4)
[] (bus_for_each_dev) from [] (driver_attach+0x24/0x28)
[] (driver_attach) from [] (bus_add_driver+0x1a0/0x218)
[] (bus_add_driver) from [] (driver_register+0x80/0x100)
[] (driver_register) from [] (__platform_driver_register+0x48/0x50)
[] (__platform_driver_register) from [] (fsl_dspi_driver_init+0x1c/0x20)
[] (fsl_dspi_driver_init) from [] (do_one_initcall+0x4c/0x174)
[] (do_one_initcall) from [] (kernel_init_freeable+0x144/0x1d8)
[] (kernel_init_freeable) from [] (kernel_init+0x10/0x114)
[] (kernel_init) from [] (ret_from_fork+0x14/0x2c)Cc:
Fixes: 5ee67b587a2b ("spi: dspi: clear SPI_SR before enable interrupt")
Signed-off-by: Krzysztof Kozlowski
Signed-off-by: Mark Brown
Signed-off-by: Greg Kroah-Hartman -
commit 22d71a5097ec7059b6cbbee678a4f88484695941 upstream.
Intel Ice Lake SPI host controller follows the Intel Cannon Lake but the
PCI IDs are different. Add the new PCI IDs to the driver supported
devices list.Signed-off-by: Mika Westerberg
Signed-off-by: Jarkko Nikula
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman -
commit 563a53f3906a6b43692498e5b3ae891fac93a4af upstream.
On non-OF systems spi->controlled_data may be NULL. This causes a NULL
pointer derefence on dm365-evm.Signed-off-by: Bartosz Golaszewski
Signed-off-by: Mark Brown
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman
03 Aug, 2018
3 commits
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[ Upstream commit ded5fa4e8bac25612caab8f0822691308a28a552 ]
If devm_spi_register_master() fails in meson_spicc_probe(),
spicc->core is left undisabled. The patch fixes that.Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Alexey Khoroshilov
Reviewed-by: Neil Armstrong
Signed-off-by: Mark Brown
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 7e48e23a1f4a50f93ac1073f1326e0a73829b631 ]
If pm_runtime_get_sync() fails we should call pm_runtime_put_noidle().
This is probably not a critical fix as we should only hit this when
things are broken elsewhere.Signed-off-by: Tony Lindgren
Signed-off-by: Mark Brown
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman -
[ Upstream commit 0921e11e1e12802ae0a3c19cb02e33354ca51967 ]
According to section 59.2.4 MSIOF Receive Mode Register 1 (SIRMDR1) in
the R-Car Gen3 datasheet Rev.1.00, the value of the SIRMDR1.SYNCAC bit
must match the value of the SITMDR1.SYNCAC bit. However,
sh_msiof_spi_setup() changes only the latter.Fix this by updating the SIRMDR1 register like the SITMDR1 register,
taking into account register bits that exist in SITMDR1 only.Reported-by: Renesas BSP team via Yoshihiro Shimoda
Fixes: 7ff0b53c4051145d ("spi: sh-msiof: Avoid writing to registers from spi_master.setup()")
Signed-off-by: Geert Uytterhoeven
Reviewed-by: Simon Horman
Signed-off-by: Mark Brown
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
