22 Apr, 2020
1 commit
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Add the ID of the resources for the V2X MUs in order
for the MU to be powered up.Signed-off-by: Stéphane Dion
09 Apr, 2020
1 commit
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Add the M4 core reset for i.MX8MQ, then we could use reset API
to start/stop M4.Reviewed-by: Richard Zhu
Signed-off-by: Peng Fan
03 Apr, 2020
1 commit
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Add macro for the SNVS clock of the i.MX8MN.
Signed-off-by: Horia Geantă
Acked-by: Rob Herring
Signed-off-by: Shawn Guo
(cherry picked from commit d2d46dfaa72b41b4d6adf6ef1068ee00a51ba0fc)
[changed clock id]
Signed-off-by: Horia Geantă
Reviewed-by: Iuliana Prodan
27 Mar, 2020
1 commit
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There is hardware issue: TKT0535653
SDMA3 can't work without setting AUDIOMIX_CLKEN0[SDMA2] (bit-26) to 1The workaround is:
As the reset state of AUDIOMIX_CLKEN0[SDMA2] is enabled,
we just need to keep it on as reset state, don't touch it
in kernel, then every thing is same as before, if we register
the clock in clk-audiomix, then kernel will try to disable
it in idle.Signed-off-by: Shengjiu Wang
Reviewed-by: Daniel Baluta
Reviewed-by: Jacky Bai
Reviewed-by: Robin Gong
14 Mar, 2020
1 commit
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The Security Violation module requires SC API for the SECO, RM, MISC
and IRQ.This patch does:
- imx-scu-irq: Allow reuse of imx_scu_irq_get_status
- seco:
- Add imx_sc_seco_secvio_enable
- Add imx_sc_seco_secvio_config
- Add imx_sc_seco_secvio_dgo_configSigned-off-by: Franck LENORMAND
08 Mar, 2020
1 commit
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Merge Linux stable release v5.4.24 into imx_5.4.y
* tag 'v5.4.24': (3306 commits)
Linux 5.4.24
blktrace: Protect q->blk_trace with RCU
kvm: nVMX: VMWRITE checks unsupported field before read-only field
...Signed-off-by: Jason Liu
Conflicts:
arch/arm/boot/dts/imx6sll-evk.dts
arch/arm/boot/dts/imx7ulp.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
drivers/clk/imx/clk-composite-8m.c
drivers/gpio/gpio-mxc.c
drivers/irqchip/Kconfig
drivers/mmc/host/sdhci-of-esdhc.c
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
drivers/net/can/flexcan.c
drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
drivers/net/ethernet/mscc/ocelot.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
drivers/net/phy/realtek.c
drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
drivers/perf/fsl_imx8_ddr_perf.c
drivers/tee/optee/shm_pool.c
drivers/usb/cdns3/gadget.c
kernel/sched/cpufreq.c
net/core/xdp.c
sound/soc/fsl/fsl_esai.c
sound/soc/fsl/fsl_sai.c
sound/soc/sof/core.c
sound/soc/sof/imx/Kconfig
sound/soc/sof/loader.c
22 Feb, 2020
1 commit
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Add second USB PHY power domain
Reviewed-by: Peter Chen
Signed-off-by: Frank Li
18 Feb, 2020
1 commit
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Update sc ctrl interfaces to sync with scu (Build 4215, Commit 21252ec7).
Reviewed-by: Richard Zhu
Signed-off-by: Fugang Duan
13 Feb, 2020
3 commits
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This patch adds "media_ldb_root_clk" clock for
the LDB in the MEDIAMIX subsystem.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
This patch adds DISP2 pixel clock for the second instance of LCDIFv3
in the MEDIAMIX subsystem.Reviewed-by: Sandor Yu
Signed-off-by: Liu Ying -
Add driver for imx8dxl based on previous SCU implementations.
Signed-off-by: Teo Hall
Reviewed-by: Anson Huang
23 Jan, 2020
1 commit
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commit 4881873f4cc1460f63d85fa81363d56be328ccdc upstream.
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
Signed-off-by: Martin Blumenstingl
Signed-off-by: Kevin Hilman
Signed-off-by: Greg Kroah-Hartman
21 Jan, 2020
1 commit
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The root clock slice at 0xbf00 is media_ldb clock, not csi_phy2_ref,
so correct it.Signed-off-by: Jacky Bai
Reviewed-by: Liu Ying
20 Jan, 2020
1 commit
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The audiomix MFD driver registers some devices, one of which maps correctly to
a reset controller type. This driver registers a reset controller for that.
For now, only the EARC specific resets are added.Signed-off-by: Abel Vesa
Reviewed-by: Leonard Crestez
19 Jan, 2020
3 commits
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Add hdmimix clk driver for imx8mp.
Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai -
Add hdmi reset driver.
According hdmimix submodues.
Group hdmimix reset bits to eight reset domains as followed:
IMX_HDMIMIX_HDMI_TX_RESET
IMX_HDMIMIX_HDMI_PHY_RESET
IMX_HDMIMIX_HDMI_PAI_RESET
IMX_HDMIMIX_HDMI_PVI_RESET
IMX_HDMIMIX_HDMI_TRNG_RESET
IMX_HDMIMIX_IRQ_STEER_RESET
IMX_HDMIMIX_HDMI_HDCP_RESET
IMX_HDMIMIX_LCDIF_RESETSigned-off-by: Sandor Yu
Reviewed-by: Robby Cai -
27M HDMI clock have replaced by 24M in IP.
Fix HDMI AXI clk parent issue.Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai
13 Jan, 2020
4 commits
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A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.The A53 CCM clk root should only be used when need to change ARM PLL
frequency.Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan -
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.The A53 CCM clk root should only be used when need to change ARM PLL
frequency.Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan -
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.The A53 CCM clk root should only be used when need to change ARM PLL
frequency.Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan -
A53 CCM clk root only accepts input up to 1GHz, however
the A53 core could run above 1GHz which voliates the CCM limitation.There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.The A53 CCM clk root should only be used when need to change ARM PLL
frequency.Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Enable arm_pll_out to avoid disable the clock when set a53 core parent.Fixes db27e40b27f18 ("clk: imx8mq: Add the missing ARM clock")
Reviewed-by: Jacky Bai
Signed-off-by: Peng Fan
26 Dec, 2019
2 commits
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Add i.MX8MP SoC & board basic DT support.
Signed-off-by: Anson Huang
Signed-off-by: Fancy Fang
Signed-off-by: Han Xu
Signed-off-by: Abel Vesa
Signed-off-by: Jacky Bai
Signed-off-by: Joakim Zhang
Signed-off-by: Clark Wang
Signed-off-by: Peng Fan
Signed-off-by: Haibo Chen
Signed-off-by: Shengjiu Wang
Signed-off-by: Ella Feng
Signed-off-by: Zhou Peng
Signed-off-by: Viorel Suman
Reviewed-by: Peng Fan -
Add support for i.MX8MP clock driver.
Signed-off-by: Anson Huang
Signed-off-by: Fugang Duan
Signed-off-by: Viorel Suman
Signed-off-by: Abel Vesa
Signed-off-by: Fancy Fang
Reviewed-by: Peng Fan
23 Dec, 2019
1 commit
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Current i2c4/uart1 clocks ID have conflict with pwm2/pwm3,
correct them.Reviewed-by: Anson Huang
Signed-off-by: Fugang Duan
02 Dec, 2019
6 commits
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* reset/next: (12 commits)
reset: Kconfig: use 'ARCH_MXC' for reset dispmix
reset: imx8m: Correct clock name for dispmix driver
reset: gpio-reset: add pinctrl comsuer header file
reset: imx7: add the clkreq reset for imx8m
dt-bindings: reset: imx7: add clkreq reset used by the l1ss on imx8m
... -
* pinctrl/next: (18 commits)
pinctrl: s32v234: Add FlexCAN pins to S32V234 driver
dt-bindings: pinctrl: s32v234: Add defines for all pins
dt-bindings: pinctrl: s32v234: Add macros for MSCR and config pairs
pinctrl: s32v234: Remove s32v234_pins enum
dt-bindings: pinctrl: s32v234: Add macros for MSCR/IMCR numbers
... -
* pcie/next: (40 commits)
LF-128 PCI: imx: turn off the clocks and regulators when link is down
PCI: imx: add the imx pcie ep verification solution
misc: pci_endpoint_test: Add the layerscape PCIe GEN4 EP device support
PCI: mobiveil: Add workaround for unsupported request error
PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape SoCs
... -
* firmware/next: (15 commits)
firmware: imx: Allow imx dsp to be selected as module
LF-202-4 firmware: imx: scu-pd: ignore power domain not owned
LF-202-2 firmware: imx: add resource management api
LF-202-1 firmware: imx: scu: use hvc for dom0
MLK-22984 firmware: imx: imx-scu-irq: fix RCU complains after M4 partition reset
... -
* dts/next: (765 commits)
arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the Felix CPU port
arm64: dts: fsl: ls1028a: Specify that the Felix port 4 runs at 2.5Gbps
arm64: dts: fsl: Drop "compatible" string from Felix switch
arm64: dts: fsl: Specify phy-mode for CPU ports
LF-261: arm64: dts: imx8mq: Set parent clock for IMX8MQ_CLK_AUDIO_AHB
... -
* origin/clock/s32: (9 commits)
clk: s32v234: Enable FlexCAN clock
clk: s32v234: Add definitions for CAN clocks
clk: s32v234: Initial enet clk support
clk: s32v234: Add dfs clk
clk: Enable SDHC clock for S32V234
...
29 Nov, 2019
4 commits
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Define macros which will indicate the clock signals obtained after
auxiliary clock 6 source selection and division (CAN_CLK) respectively.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Stefan-Gabriel Mirea -
Add macros for MSCR register numbers, configuration for these registers
and pairs of MSCR numbers and values for all currently supported
peripherals in the Auto Linux BSP.Signed-off-by: Mihaela Martinas
Signed-off-by: Ghennadi Procopciuc
Signed-off-by: Cristian Tomescu
Signed-off-by: Larisa Grigore
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Grigore Lupescu
Signed-off-by: Eddy Petrișor
Signed-off-by: Cosmin Oprea
Signed-off-by: Chircu-Mare Bogdan-Petru
Signed-off-by: Costin Carabas
Signed-off-by: Catalin Udma
Signed-off-by: Andrei Trandafir
Signed-off-by: Stefan-Gabriel Mirea
Reviewed-by: Leonard Crestez -
Define macros for the combinations of MSCR numbers and values to be
written into those registers. These will be used together in 'fsl,pins'
properties of pinctrl group dts nodes.Signed-off-by: Mihaela Martinas
Signed-off-by: Stefan-Gabriel Mirea
Reviewed-by: Leonard Crestez -
The values of the s32v234_pins enum from pinctrl-s32v234.c will be moved
to s32v234-pinctrl.h to avoid using magic numbers in ENET configuration
definitions.Signed-off-by: Stefan-Gabriel Mirea
Reviewed-by: Leonard Crestez
25 Nov, 2019
6 commits
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Enable the imx8qm/qxp pcie support.
Verified on the imx8qxp mek board.Signed-off-by: Richard Zhu
-
Add ethernet clocks and dependencies (sys_pll, arm_pll)
Based on ALB v4.19.31_bsp23.0_rc2
Signed-off-by: Leonard Crestez
Reviewed-by: Fugang Duan -
Enable the clocks needed for uSDHC support on Treerunner.
Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Larisa Grigore
Signed-off-by: Stefan-Gabriel Mirea -
Enable the clocks needed for LINFlexD UART support on Treerunner and make
use of them in the LINFlexD driver.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Adrian.Nitu
Signed-off-by: Larisa Grigore
Signed-off-by: Iustin Dumitrescu
Signed-off-by: Stefan-Gabriel Mirea
Signed-off-by: Leonard Crestez -
Add DT bindings documentation for the upcoming S32V234 clk driver. Add
s32v234-clock.h header, which is referred in MC_CGM documentation.Signed-off-by: Stoica Cosmin-Stefan
Signed-off-by: Stefan-Gabriel Mirea -
This clock is a high precision clock on imx8mq-evk board that will be used by
HDMI phy.Signed-off-by: Laurentiu Palcu
