26 Jan, 2008

2 commits


25 Jan, 2008

2 commits


16 Jan, 2008

1 commit

  • The compiler team did the hard work for this distilling a problem in
    large fortran application which showed up when applied to a 290MB input
    data set down to this instruction:

    ldfd f34=[r17],-8

    Which they noticed incremented r17 by 0x10 rather than decrementing it
    by 8 when the value in r17 caused an unaligned data fault. I tracked
    it down to some bad instruction decoding in unaligned.c. The code
    assumes that the 'x' bit can determine whether the instruction is
    an "ldf" or "ldfp" ... which it is for opcode=6 (see table 4-29 on
    page 3:302 of the SDM). But for opcode=7 the 'x' bit is irrelevent,
    all variants are "ldf" instructions (see table 4-36 on page 3:306).

    Note also that interpreting the instruction as "ldfp" means that the
    "paired" floating point register (f35 in the example here) will also
    be corrupted.

    Signed-off-by: Tony Luck

    Luck, Tony
     

04 Jan, 2008

1 commit

  • Montecito and Montvale behaves slightly differently than previous
    Itanium processors, resulting in the MCA due to a failed PIO read
    to sometimes surfacing outside the nofault code. This code is
    based on discussions with Intel CPU architects and verified at
    customer sites.

    Signed-off-by: Russ Anderson
    Signed-off-by: Tony Luck

    Russ Anderson
     

20 Dec, 2007

7 commits

  • Currently CMCI mask of hot-added CPU is always disabled after CPU hotplug.
    We should adjust this mask depending on CMC polling state.

    Signed-off-by: Hidetoshi Seto
    Signed-off-by: Satoru Takeuchi
    Signed-off-by: Tony Luck

    Hidetoshi Seto
     
  • This fixes an unused variable warning in mm/vmalloc.c.

    Tony: also fix resulting fallout in uncached.c with a
    typo in args to flush_tlb_kernel_range().

    Signed-off-by: Jan Beulich
    Signed-off-by: Tony Luck

    Jan Beulich
     
  • Access to elfcorehdr_addr needs to be guarded by #if CONFIG_PROC_FS
    as well as the existing #if guards.

    Fixes the following build problem:

    arch/ia64/hp/common/built-in.o: In function
    `sba_init':arch/ia64/hp/common/sba_iommu.c:2043: undefined reference to `elfcorehdr_addr'
    :arch/ia64/hp/common/sba_iommu.c:2043: undefined reference to `elfcorehdr_addr'

    Signed-off-by: Simon Horman
    Signed-off-by: Tony Luck

    Simon Horman
     
  • The Altix shub2 BTE error detail bits are in a different location
    than on shub1. The current code does not take this into account
    resulting in all shub2 BTE failures mapping to "unknown".

    This patch reads the error detail bits from the proper location,
    so the correct BTE failure reason is returned for both shub1
    and shub2.

    Signed-off-by: Russ Anderson
    Signed-off-by: Tony Luck

    Russ Anderson
     
  • This patch removes the following assembler warning messages.

    AS arch/ia64/kernel/head.o
    arch/ia64/kernel/head.S: Assembler messages:
    arch/ia64/kernel/head.S:1179: Warning: Use of 'ld8' violates RAW dependency 'CR[PTA]' (data)
    arch/ia64/kernel/head.S:1179: Warning: Only the first path encountering the conflict is reported
    arch/ia64/kernel/head.S:1178: Warning: This is the location of the conflicting usage
    arch/ia64/kernel/head.S:1180: Warning: Use of 'ld8' violates RAW dependency 'CR[PTA]' (data)
    arch/ia64/kernel/head.S:1180: Warning: Only the first path encountering the conflict is reported
    arch/ia64/kernel/head.S:1178: Warning: This is the location of the conflicting usage
    :
    arch/ia64/kernel/head.S:1213: Warning: Use of 'ldf.fill.nta' violates RAW dependency 'CR[PTA]' (data)
    arch/ia64/kernel/head.S:1213: Warning: Only the first path encountering the conflict is reported
    arch/ia64/kernel/head.S:1178: Warning: This is the location of the conflicting usage

    Signed-off-by: Hidetoshi Seto
    Signed-off-by: Tony Luck

    Hidetoshi Seto
     
  • This patch removes the following compiler warning messages.

    CC arch/ia64/kernel/irq_ia64.o
    arch/ia64/kernel/irq_ia64.c: In function 'create_irq':
    arch/ia64/kernel/irq_ia64.c:343: warning: 'domain.bits[0u]' may be used uninitialized in this function
    arch/ia64/kernel/irq_ia64.c: In function 'assign_irq_vector':
    arch/ia64/kernel/irq_ia64.c:203: warning: 'domain.bits[0u]' may be used uninitialized in this function

    Signed-off-by: Kenji Kaneshige
    Signed-off-by: Tony Luck

    Kenji Kaneshige
     
  • I tried to upgrade an IA32 chroot on my IA64 to a new glibc with TLS.
    It kept dying because set_thread_area was returning -ESRCH
    (bugs.debian.org/451939).

    I instrumented arch/ia64/ia32/sys_ia32.c:get_free_idx() and ended up
    seeing output like

    [pid] idx desc->a desc->b
    -----------------------------
    [2710] 0 -> c6b0ffff 40dff31b
    [2710] 1 -> 0 0
    [2710] 2 -> 0 0

    [2710] 0 -> c6b0ffff 40dff31b
    [2710] 1 -> c6b0ffff 40dff31b
    [2710] 2 -> 0 0

    [2711] 0 -> c6b0ffff 40dff31b
    [2711] 1 -> c6b0ffff 40dff31b
    [2711] 2 -> 48c0ffff 40dff317

    which suggested to me that TLS pointers were surviving exec() calls,
    leading to GDT pointers filling up and the eventual failure of
    get_free_idx().

    I think the solution is flushing the tls array on exec.

    Signed-Off-By: Ian Wienand
    Signed-off-by: Tony Luck

    Ian Wienand
     

19 Dec, 2007

5 commits

  • The ia64 oops message doesn't include the kernel version, which
    makes it hard to automatically categorize oops messages scraped
    from mailing lists and bug databases.

    Signed-off-by: Tony Luck

    Luck, Tony
     
  • s/addres/address/
    s/performanc/performance/

    Signed-off-by: Joe Perches
    Signed-off-by: Tony Luck

    Joe Perches
     
  • Improve performance of memory allocations on ia64 by avoiding a global TLB
    purge to purge a single page from the file cache. This happens whenever we
    evict a page from the buffer cache to make room for some other allocation.

    Test case: Run 'find /usr -type f | xargs cat > /dev/null' in the
    background to fill the buffer cache, then run something that uses memory,
    e.g. 'gmake -j50 install'. Instrumentation showed that the number of
    global TLB purges went from a few millions down to about 170 over a 12
    hours run of the above.

    The performance impact is particularly noticeable under virtualization,
    because a virtual TLB is generally both larger and slower to purge than
    a physical one.

    Signed-off-by: Christophe de Dinechin
    Signed-off-by: Tony Luck

    de Dinechin, Christophe (Integrity VM)
     
  • Convert ia64's ia32 support from nopage to fault.

    Signed-off-by: Nick Piggin
    Signed-off-by: Andrew Morton
    Signed-off-by: Tony Luck

    Nick Piggin
     
  • This patch removes some redundant code in the function setup_sigcontext().

    The registers ar.ccv,b7,r14,ar.csd,ar.ssd,r2-r3 and r16-r31 are not
    restored in restore_sigcontext() when (flags & IA64_SC_FLAG_IN_SYSCALL) is
    true. So we don't need to zero those variables in setup_sigcontext().

    Signed-off-by: Shi Weihua
    Signed-off-by: Andrew Morton
    Signed-off-by: Tony Luck

    Shi Weihua
     

08 Dec, 2007

12 commits


15 Nov, 2007

1 commit

  • i386 and x86-64 registers System RAM as IORESOURCE_MEM | IORESOURCE_BUSY.

    But ia64 registers it as IORESOURCE_MEM only.
    In addition, memory hotplug code registers new memory as IORESOURCE_MEM too.

    This difference causes a failure of memory unplug of x86-64. This patch
    fixes it.

    This patch adds IORESOURCE_BUSY to avoid potential overlap mapping by PCI
    device.

    Signed-off-by: Yasunori Goto
    Signed-off-by: Badari Pulavarty
    Cc: Luck, Tony"
    Cc: Thomas Gleixner
    Cc: Ingo Molnar
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Yasunori Goto
     

10 Nov, 2007

4 commits

  • On Altix (sn2) machines the "Error parsing MADT" message is
    misleading because the lack of IOSAPIC entries is expected.

    Since I am sure someone will ask, I have been told that
    the chance of this changing anytime soon is close to nil.

    Signed-off-by: George Beshers
    Signed-off-by: Tony Luck

    George Beshers
     
  • Newer Itanium versions have added additional processor feature set
    bits. This patch prints all the implemented feature set bits. Some
    bit descriptions have not been made public. For those bits, a generic
    "Feature set X bit Y" message is printed. Bits that are not implemented
    will no longer be printed.

    Signed-off-by: Russ Anderson
    Signed-off-by: Tony Luck

    Russ Anderson
     
  • Fix the problem that redirect hit bit in I/O SAPIC RTE is set even
    when it must be disabled (e.g. nointroute boot option is set, CPU
    hotplug is enabled or percpu vector is enabled).

    Signed-off-by: Kenji Kaneshige
    Signed-off-by: Tony Luck

    Kenji Kaneshige
     
  • Currently, XPC's heartbeat timer function runs on whatever CPU modprobe/insmod
    ran on when XPC was started. To avoid the heartbeat from being delayed for
    long periods the timer function must run on CPU 0.

    N.B. Altix doesn't currently allow cpu0 to be taken offline, so this is
    safe for now. This code must be revised when offline of cpu0 is enabled.

    Signed-off-by: Dean Nelson
    Signed-off-by: Tony Luck

    Dean Nelson
     

07 Nov, 2007

5 commits

  • Clean up /proc/interrupts output on the system that has 10 or more
    CPUs.

    Signed-off-by: Kenji Kaneshige
    Signed-off-by: Tony Luck

    Kenji Kaneshige
     
  • When the CPE handler encounters too many CPEs (such as a solid single
    bit memory error), it sets up a polling timer and disables the CPE
    interrupt (to avoid excessive overhead logging the stream of single
    bit errors). disable_irq_nosync() calls chip->disable() to provide
    a chipset specifiec interface for disabling the interrupt. This patch
    adds the Altix specific support to disable and re-enable the CPE interrupt.

    Signed-off-by: Russ Anderson (rja@sgi.com)
    Signed-off-by: Tony Luck

    Russ Anderson
     
  • No need to print "McKinley Errata 9 workaround not needed; disabling it"
    on every non-McKinley Itanium, which at this point is almost all of them.

    Signed-off-by: Russ Anderson (rja@sgi.com)
    Signed-off-by: Tony Luck

    Russ Anderson
     
  • If you build the kernel `in-place' then do a git update, git
    complains about arch/ia64/kernel/gate.lds being modified and
    untracked.

    Add that (generated) file to a .gitignore file.

    Signed-off-by: Peter Chubb
    Signed-off-by: Tony Luck

    Peter Chubb
     
  • There is a section mismatch when building CONFIG_FLATMEM=y kernels
    that also have CONFIG_HOTPLUG_CPU=y

    WARNING: vmlinux.o(.text+0x5a902): Section mismatch: reference to \
    .init.text:__alloc_bootmem (between 'per_cpu_init' and 'count_pages')

    The issue occurs because per_cpu_init() in mm/contig.c is
    marked __cpuinit (which is #define'd to nothing on a hot
    plug cpu configuration) call __alloc_bootmem() (which is
    an __init function). The usage is actually safe because
    the __alloc_bootmem() is inside an "if (first_time)" test
    so that the call is only made while it is still legal to
    do so.

    But the warning is irritating. Move the allocation to
    find_memory().

    Signed-off-by: Tony Luck

    Tony Luck