08 Jun, 2017
40 commits
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That's pf1550's internal interrupt, usless for charger.
Signed-off-by: Robin Gong
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Do not probe if the device node is not correct in dts.
Signed-off-by: Robin Gong
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check OTP_SW2_DVS_ENB bit for the different voltage list while SW2
regulator registered.Signed-off-by: Robin Gong
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Enable ONKEY wakeup interrupt before suspend, and remove usless marocs.
Signed-off-by: Robin Gong
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add ".use_ack" ..etc for pf1550 irq, since we have to clear irq status in
pf1550, else no any more interrupt trigged.Signed-off-by: Robin Gong
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The voltage of LDO1 and LDO3 are not linear, use voltage_table instead,so
add new ops for them. Meanwhile, correct 12500uV for one step of SW1/SW2
rather than 125000uV.Signed-off-by: Robin Gong
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Correct num_regs of regmap_irq_chip structure, otherwise request irq
failed.Signed-off-by: Robin Gong
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Add pf1550_onkey driver, so that POWERON key can link to pf1550 instead of
i.mx6ul.Signed-off-by: Robin Gong
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Add basic pf1550 charger driver.
Signed-off-by: Robin Gong
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Add basic pf1550 regulator driver.
Signed-off-by: Robin Gong
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Add basic pf1550 mfd driver.
Signed-off-by: Robin Gong
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Fix coverity CID 17574 uncheck return value.
Signed-off-by: Guoniu.Zhou
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Add pinctrl driver support for i.MX6SLL.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping -
Add clock driver for i.MX6SLL.
Signed-off-by: Anson Huang
Signed-off-by: Bai Ping
Signed-off-by: Frank Li -
In order to pass the pcie gen2 compliance tests,
the external oscillator is mandatory required by
imx6 legacy platforms.
add the external osc support by this patch.
- pll6 should be set bypass mode.
- src of the pll6_bypass should be lvds_clk1
- adjust the swing/deemphase value
- re-configure the phy if the external 100Mhz
differential osc is used. Because that phy used
the 125Mhz before.Signed-off-by: Richard Zhu
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When the external oscillator is used as pcie ref clk.
the below configurations should done.
- set the lvds_clk1 as input
- set the source of the pll6_bypass to be lvds_clk1
- set the pll6 to be bypass mode.Signed-off-by: Richard Zhu
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BCMDHD_SDIO needs to be tristate for the correct dependency
of MMC core subsystem.
And the old driver buildin mode is static defined by DRIVER_TYPE.
Fix it to depend on CONFIG_BCMDHD_SDIO.Signed-off-by: Dong Aisheng
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i.MX6ULL has errata ERR010450, which says due to SOC I/O timing
limit, eMMC HS200 and SD/SDIO 3.0 SDR104 at 1.8v can only work
below or equal to 150MHz. And eMMC DDR52 and SD/SDIO DDR50 at
1.8v can only work below or equal to 45MHz.This patch add this limit for imx6ull.
Signed-off-by: Haibo Chen
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For imx6ul PHY, when the system enters suspend, its 1p1 is off by default,
that may cause the PHY get inaccurate USB DP/DM value. If the USB wakeup
is enabled at this time, the unexpected wakeup may occur when the system
enters suspend.In this patch, when the vbus is there, we enable weak 1p1 during the PHY
suspend API, in that case, the USB DP/DM will be accurate for USB PHY,
then unexpected usb wakeup will not be occurred, especially for the USB
charger is connected scenario. The user needs to enable PHY wakeup for
USB wakeup function using below setting.echo enabled > /sys/devices/platform/soc/2000000.aips-bus/20c9000.usbphy
/power/wakeupCc: Shaojun Wang
Cc: Anson Huang
Signed-off-by: Peter Chen -
On imx6qp sabresd rev b board, there is a standalone
external oscilator, used to provided the clks for
imx6qp pcie.Add one regulator into pcie node, let the ext osc work.
Signed-off-by: Richard Zhu
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Enable OOB feature for MX6Q/DL SDB, MX6SL EVK, MX6SX SDB, MX7D SDB boards.
NOTE: The performance optimization option CONFIG_BCM4339 is disabled
by default due to a WiFi driver issue that it breaks MX6SL EVK.If user want to test performance on the above platforms (except MX6SL EVK),
CONFIG_BCM4339 has to be enabled manually.Signed-off-by: Dong Aisheng
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The patch is delivered by Cypress to add OOB switch interface
and a P2P stability fix.Whether to enable OOB is controlled by the gpios property under
bcmdhd_wlan_0 node.
e.g.
bcmdhd_wlan_0: bcmdhd_wlan@0 {
compatible = "android,bcmdhd_wlan";
gpios = ; /* WL_HOST_WAKE */
wlreg_on-supply = ;
};If valid gpios property found, then driver will consider to use
OOB feature.Signed-off-by: Dong Aisheng
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For Mega/Mix enabled SoCs like MX7D and MX6SX, uSDHC will lost power in
LP mode no matter whether the MMC_KEEP_POWER flag is set or not.
This may cause state misalign between kernel and HW, especially for
SDIO3.0 WiFi cards.
e.g. SDIO WiFi driver usually will keep power during system suspend.
And after resume, no card re-enumeration called.
But the tuning state is lost due to Mega/Mix.
Then CRC error may happen during next data transfer.So we should always fire a mmc_retune_needed() for such type SoC
to tell MMC core retuning is needed for next data transfer.Signed-off-by: Dong Aisheng
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On i.MX6ULL, when the CPU freq is running at 198MHz or 396MHz, the system will
enter low bus mode if no device need high bus mode. The first time the system
entering low bus mode, CPU freq will be set to 24MHz, if cpufreq change the CPU
freq from 198MHz(396MHz) to 396MHz(198MHz), the CPU freq will be set to 198MHz or
396 MHz. At this time, if the CPU enter low power idle, system will hang.Signed-off-by: Bai Ping
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Since the eink panel will not be re-initialized after exit DSM(deep sleep mode),
it will depend on the last update content so we need keep the associated working
buffer content during DSM. The patch moves the initialization of working buffer
to probe() function and ensure it's just be initialized once and thus its
content will be kept.The patch shall fix the following issue:
The codes as follows in unit test for clearing screen does not take effect
when enter/exit DSM.---
printf("Blank screen\n");
memset(fb, 0xFE, screen_info.xres_virtual*screen_info.yres*screen_info.bits_per_pixel/8);
update_to_display(0, 0, screen_info.xres, screen_info.yres,
wave_mode, TRUE, 0);
---Signed-off-by: Robby Cai
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When VPU runs at 396MHz, VDDSOC_CAP's voltage
should be set to 1.275V for all set-points,
add VPU clock rate check to support this case.Signed-off-by: Anson Huang
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When i.MX6QP with speed grading fuse blown to 1.2GHz,
VPU should run at 396MHz, add this support.Signed-off-by: Anson Huang
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On i,MX6SL, no NUM and DENUM register, so this PLL should not
be registered as IMX_PLLV3_GENERIC type PLL, it should be
registered as IMX_PLLV3_SYSV2.Signed-off-by: Bai Ping
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Added clock enable and disable to the probe and remove functions
where appropriate.Signed-off-by: Dan Douglass
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According the the latest datasheet, we updated the lowest
OPP to 198MHz. So we need to update the cpufreq code to fix
the syttem hang issue when run 'cpufreq-info' in low bus mode
on i.MX6ULL.Signed-off-by: Bai Ping
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Enable DCP support for imx6 series.
Signed-off-by: Dan Douglass
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running following vte stress test will meet "mx6s-csi 21c4000.csi: mx6s_csi_irq_handler Rx fifo overflow"
and cannot be stopped to capture again.i=0; while [ $i -lt 3000 ];do v4l2_capture_emma -D /dev/video1 -C 2 -M 0 -J 30,4 -W 640 -H 480;i=`expr $i + 1`;done
This patch adds the same handling as BIT_HRESP_ERR_INT for BIT_RFF_OR_INT
(RxFiFo OverFlow) to reset CSI as a recovery.Signed-off-by: Robby Cai
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As i.MX6's PLL2 also support a fractional-N
synthesizer, so we need to consider the NUM
and DENOM's value to get a correct rate, as
fraction may be used in some cases.Remove round_rate and set_rate for PLL2, as
it is NOT allowed to be changed in kernel
dynamically, otherwise, PFDs and DDR may NOT
work normally, it normally should be changed
in u-boot before DDR is enabled.Signed-off-by: Anson Huang
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Add fb name check function pwm_backlight_check_fb_name(),
pwm driver can banding to fb with fb name when driver working
in device tree architecture.Signed-off-by: Sandor Yu
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i.MX6SX LDB will connect to LCDIF2.
And LCDIF2 pixel clock can not re-parent when it's on.
So default setting clock parent to ldb_di0.Signed-off-by: Sandor Yu
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On i.MX6ULL, when the system entering the low bus mode, system will enter
low power run mode in which the cpufreq is at 24MHz. If we run
'cpufreq-info' until, the cpu frequency will be change from 24MHz to 99MHz,
this will lead to system enter low power idle wrong, and system will hang
in low power idle.Add the ARM core clock handling code to fix this issue.
Signed-off-by: Bai Ping
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Add the sanity check for drect's width and height in
pxp_set_scaling() to avoid div0 exception.Signed-off-by: Fancy Fang
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The dynamicly allocated 'pseudo_palette' area should be
freed when unused to avoid memory leak.Signed-off-by: Fancy Fang
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Refine the 'fb_info' field in 'mxsfb_info' that change this
field to be a pointer which can reduce the 'mxsfb_info' size.
Besides, store the 'host' data to fb_info->par to replace the
unnecessary 'to_imxfb_host' macro.Signed-off-by: Fancy Fang
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The function 'platform_set_drvdata' will be called twice
during the probing stage. And the second calling is not
good and not necessary.Signed-off-by: Fancy Fang
