31 Jan, 2019
1 commit
-
After finding a "firmware" dt node stratix10 tries to match it's
compatible string with it. To do so it's calling of_find_matching_node()
which already takes care of decreasing the refcount on the "firmware"
node. We are then incorrectly decreasing the refcount on that node
again.This patch removes the unwarranted call to of_node_put().
Fixes: e7eef1d7633a ("fpga: add intel stratix10 soc fpga manager driver")
Signed-off-by: Nicolas Saenz Julienne
Acked-by: Alan Tull
Acked-by: Moritz Fischer
[atull: remove unnecessary braces]
Signed-off-by: Greg Kroah-Hartman
04 Jan, 2019
1 commit
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Nobody has actually used the type (VERIFY_READ vs VERIFY_WRITE) argument
of the user address range verification function since we got rid of the
old racy i386-only code to walk page tables by hand.It existed because the original 80386 would not honor the write protect
bit when in kernel mode, so you had to do COW by hand before doing any
user access. But we haven't supported that in a long time, and these
days the 'type' argument is a purely historical artifact.A discussion about extending 'user_access_begin()' to do the range
checking resulted this patch, because there is no way we're going to
move the old VERIFY_xyz interface to that model. And it's best done at
the end of the merge window when I've done most of my merges, so let's
just get this done once and for all.This patch was mostly done with a sed-script, with manual fix-ups for
the cases that weren't of the trivial 'access_ok(VERIFY_xyz' form.There were a couple of notable cases:
- csky still had the old "verify_area()" name as an alias.
- the iter_iov code had magical hardcoded knowledge of the actual
values of VERIFY_{READ,WRITE} (not that they mattered, since nothing
really used it)- microblaze used the type argument for a debug printout
but other than those oddities this should be a total no-op patch.
I tried to fix up all architectures, did fairly extensive grepping for
access_ok() uses, and the changes are trivial, but I may have missed
something. Any missed conversion should be trivially fixable, though.Signed-off-by: Linus Torvalds
27 Nov, 2018
5 commits
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Use platform_set_drvdata rather than dev_set_drvdata
to match the platform_get_drvdata in the _remove()
function of the platform driver.Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Use platform_get_drvdata() in remove() function of
the platform driver rather than dev_get_drvdata()
to match the platform_set_drvdata in the probe().Signed-off-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Add driver for reconfiguring Intel Stratix10 SoC FPGA devices.
This driver communicates through the Intel service layer driver
which does communication with privileged hardware (that does the
FPGA programming) through a secure mailbox.Signed-off-by: Alan Tull
Signed-off-by: Richard Gong
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Driver probing fails on non-dt platforms since of_match_device()
always returns NULL here. Add spi ids with device names and
matching driver data as an index of a map array with data for
supported devices. Add this map array and a function for mapping
spi ids to driver data. This allows driver binding to dynamically
added PS-SPI devices (e.g. when added via spi_new_device() after
hot-plugging).Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Currently registering CvP managers works only for first probed CvP
device, for all other devices it is refused due to duplicated chkcfg
sysfs entry:fpga_manager fpga3: Altera CvP FPGA Manager @0000:0c:00.0 registered
sysfs: cannot create duplicate filename '/bus/pci/drivers/altera-cvp/chkcfg'
CPU: 0 PID: 3808 Comm: bash Tainted: G O 4.19.0-custom+ #5
Call Trace:
dump_stack+0x46/0x5b
sysfs_warn_dup+0x53/0x60
sysfs_add_file_mode_ns+0x16d/0x180
sysfs_create_file_ns+0x51/0x60
altera_cvp_probe+0x16f/0x2a0 [altera_cvp]
local_pci_probe+0x3f/0xa0
? pci_match_device+0xb1/0xf0
pci_device_probe+0x116/0x170
really_probe+0x21b/0x2c0
driver_probe_device+0x4b/0xe0
bind_store+0xcb/0x130
kernfs_fop_write+0xfd/0x180
__vfs_write+0x21/0x150
? selinux_file_permission+0xdc/0x130
vfs_write+0xa8/0x1a0
? find_vma+0xd/0x60
ksys_write+0x3d/0x90
do_syscall_64+0x44/0xf0
entry_SYSCALL_64_after_hwframe+0x44/0xa9
...
altera-cvp 0000:0c:00.0: Can't create sysfs chkcfg file
fpga_manager fpga3: fpga_mgr_unregister Altera CvP FPGA Manager @0000:0c:00.0Move chkcfg creation to module init as suggested by Alan.
Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
12 Nov, 2018
4 commits
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The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
it impossible to use the ICAP interface for partial reconfiguration.This patch changes the driver to only activate PR over PCAP while the
device is actively being accessed by the driver for programming.This allows both PCAP and ICAP interfaces to be used for PR.
Signed-off-by: Mike Looijmans
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The probe function needs to verify the CvP enable bit in order to
properly determine if FPGA Manager functionality can be safely
enabled.Fixes: 34d1dc17ce97 ("fpga manager: Add Altera CvP driver")
Signed-off-by: Andreas Puhm
Signed-off-by: Anatolij Gustschin
Reviewed-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Fixes gcc '-Wunused-but-set-variable' warning:
drivers/fpga/dfl-fme-pr.c: In function 'pr_mgmt_uinit':
drivers/fpga/dfl-fme-pr.c:447:18: warning:
variable 'priv' set but not used [-Wunused-but-set-variable]Signed-off-by: YueHaibing
Acked-by: Moritz Fischer
Acked-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
If mapping the CvP BAR fails, we still can configure the FPGA via
PCI config space access. In this case the iomap pointer is NULL.
On x86_64, passing NULL address to pci_iounmap() generates
"Bad IO access at port 0x0" output with stack call trace. Fix it.Signed-off-by: Anatolij Gustschin
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
16 Oct, 2018
3 commits
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Add devm_fpga_region_create() which is the
managed version of fpga_region_create().Change current region drivers to use
devm_fpga_region_create().Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Add devm_fpga_bridge_create() which is the managed
version of fpga_bridge_create().Change current bridge drivers to use
devm_fpga_bridge_create().Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
Add devm_fpga_mgr_create() which is the managed
version of fpga_mgr_create().Change current FPGA manager drivers to use
devm_fpga_mgr_create()Signed-off-by: Alan Tull
Suggested-by: Federico Vaga
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
08 Oct, 2018
1 commit
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We want the fixes in here as well.
Signed-off-by: Greg Kroah-Hartman
30 Sep, 2018
2 commits
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fpga_bridge_dev_match() returns a FPGA bridge struct, not a
FPGA manager struct so s/manager/bridge/.Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
A couple drivers were accessing the region struct after it had been
freed. Save off the pointer to the mgr before the region struct gets
freed.Signed-off-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman
17 Sep, 2018
1 commit
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We want the bugfixes in here as well.
Signed-off-by: Greg Kroah-Hartman
12 Sep, 2018
2 commits
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Trivial fix to two spelling mistakes
"execeeded" -> "exceeded"
"Invaild" -> "Invalid"Signed-off-by: Colin Ian King
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
In case of error, the function dfl_fme_create_region() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().Fixes: 29de76240e86 ("fpga: dfl: fme: add partial reconfiguration sub feature support")
Signed-off-by: Wei Yongjun
Acked-by: Moritz Fischer
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
16 Jul, 2018
1 commit
-
We want the char-misc fixes in here as well.
Signed-off-by: Greg Kroah-Hartman
15 Jul, 2018
19 commits
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DMA memory regions are required for Accelerated Function Unit (AFU) usage.
These two ioctls allow user space applications to map user memory regions
for dma, and unmap them after use. Iova is returned from driver to user
space application via DFL_FPGA_PORT_DMA_MAP ioctl. Application needs to
unmap it after use, otherwise, driver will unmap them in device file
release operation.Each AFU has its own rb tree to keep track of its mapped DMA regions.
Ioctl interfaces:
* DFL_FPGA_PORT_DMA_MAP
Do the dma mapping per user_addr and length provided by user.
Return iova in provided struct dfl_fpga_port_dma_map.* DFL_FPGA_PORT_DMA_UNMAP
Unmap the dma region per iova provided by user.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
User Accelerated Function Unit sub feature exposes the MMIO region of
the AFU. After valid PR bitstream is programmed and the port is enabled,
then this MMIO region could be accessed.This patch adds support to enumerate the AFU MMIO region and expose it
to userspace via mmap file operation. Below interfaces are exposed to user:Sysfs interface:
* /sys/class/fpga_region///afu_id
Read-only. Indicate which PR bitstream is programmed to this AFU.Ioctl interfaces:
* DFL_FPGA_PORT_GET_INFO
Provide info to userspace on the number of supported region.
Only UAFU region is supported now.* DFL_FPGA_PORT_GET_REGION_INFO
Provide region information, including access permission, region size,
offset from the start of device fd.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common
ones which need to be supported by all feature devices drivers including
FME and AFU. This patch implements above 2 ioctls in FPGA Accelerated
Function Unit (AFU) driver.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
The port header register set is always present for port, it is mainly
for capability, control and status of the ports that AFU connected to.This patch implements header sub feature support. Below user interfaces
are created by this patch.Sysfs interface:
* /sys/class/fpga_region///id
Read-only. Port ID.Ioctl interface:
* DFL_FPGA_PORT_RESET
Reset the FPGA Port and its AFU.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch registers the port ops into the global list in the DFL
framework, and it allows other modules to use the port ops. And
This patch includes the implementation of the get_id and enable_set
ops too.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
On DFL FPGA devices, the Accelerated Function Unit (AFU), can be
reprogrammed for different functions. It connects to the FPGA
infrastructure (static FPGA region) via a Port. Port CSRs are
implemented separately from the AFU CSRs to provide control and
status of the Port. Once valid PR bitstream is programmed into
the AFU, it allows access to the AFU CSRs in the AFU MMIO space.This patch only implements basic driver framework for AFU, including
device file operation framework.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch adds compat_id support, it reuses fme manager's
compat id, as the per region compat id is actually from the
fme manager's register.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga region platform driver for FPGA Management Engine.
It register an fpga region with given fpga manager / bridge device.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga bridge platform driver for FPGA Management Engine.
It implements the enable_set callback for fpga bridge.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds compat_id support to fme manager driver, it
reads the ID from the hardware register. And it could be used
for compatibility check before partial reconfiguration.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds fpga manager driver for FPGA Management Engine (FME). It
implements fpga_manager_ops for FPGA Partial Reconfiguration function.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
Partial Reconfiguration (PR) is the most important function for FME. It
allows reconfiguration for given Port/Accelerated Function Unit (AFU).It creates platform devices for fpga-mgr, fpga-regions and fpga-bridges,
and invokes fpga-region's interface (fpga_region_program_fpga) for PR
operation once PR request received via ioctl. Below user space interface
is exposed by this sub feature.Ioctl interface:
* DFL_FPGA_FME_PORT_PR
Do partial reconfiguration per information from userspace, including
target port(AFU), buffer size and address info. It returns error code
to userspace if failed. For detailed PR error information, user needs
to read fpga-mgr's status sysfs interface.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
DFL_FPGA_GET_API_VERSION and DFL_FPGA_CHECK_EXTENSION ioctls are common
ones which need to be supported by all feature devices drivers including
FME and AFU. Userspace application can use these ioctl interfaces to get
the API info and check if specific extension is supported or not in
current driver.This patch implements above 2 ioctls in FPGA Management Engine (FME)
driver.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
The Header Register set is always present for FPGA Management Engine (FME),
this patch implements init and uinit function for header sub feature and
introduces several read-only sysfs interfaces for the capability and
status.Sysfs interfaces:
* /sys/class/fpga_region///ports_num
Read-only. Number of ports implemented* /sys/class/fpga_region///bitstream_id
Read-only. Bitstream (static FPGA region) identifier number. It contains
the detailed version and other information of this static FPGA region.* /sys/class/fpga_region///bitstream_metadata
Read-only. Bitstream (static FPGA region) meta data. It contains the
synthesis date, seed and other information of this static FPGA region.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
The FPGA Management Engine (FME) provides power, thermal management,
performance counters, partial reconfiguration and other functions. For each
function, it is packaged into a private feature linked to the FME feature
device in the 'Device Feature List'. It's a platform device created by
DFL framework.This patch adds the basic framework of FME platform driver. It defines
sub feature drivers to handle the different sub features, including init,
uinit and ioctl. It also registers the file operations for the device file.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Kang Luwei
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
The Device Feature List (DFL) is implemented in MMIO and features
are linked via the DFLs. This patch enables pcie driver to prepare
enumeration information (e.g. locations of all device feature lists
in MMIO) and use common APIs provided by the Device Feature List
framework to enumerate each feature device linked.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
This patch implements the basic framework of the driver for FPGA PCIe
device which implements the Device Feature List (DFL) in its MMIO space.
This driver is verified on Intel(R) PCIe-based FPGA DFL devices, including
both integrated (e.g. Intel Server Platform with In-package FPGA) and
discrete (e.g. Intel FPGA PCIe Acceleration Cards) solutions.Signed-off-by: Tim Whisonant
Signed-off-by: Enno Luebbers
Signed-off-by: Shiva Rao
Signed-off-by: Christopher Rauer
Signed-off-by: Zhang Yi
Signed-off-by: Xiao Guangrong
Signed-off-by: Wu Hao
Acked-by: Alan Tull
Acked-by: Moritz Fischer
Signed-off-by: Greg Kroah-Hartman -
This patch adds one common function in DFL framework. It uses
port_ops get_id callback to get port id and compare it with given
value. This function could be used as match function of the
dfl_fpga_cdev_find_port function.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman -
In some cases, other DFL driver modules may need to access some port
operations, e.g. disable / enable port for partial reconfiguration in
FME module. In order to avoid dependency between port and FME modules,
this patch introduces the dfl_fpga_port_ops support in DFL framework.
A global dfl_fpga_port_ops list is added in the DFL framework, and
it allows other DFL modules to use these port operations registered
to this list, even in virtualization case, the port platform device
is turned into VF / guest VM and hidden in host, the registered
port_ops is still usable. It resolves the dependency issues between
modules, but once get port ops API returns a valid port ops, that
means related port driver module has been module_get to prevent from
unexpected unload, and put port ops API must be invoked after use.These APIs introduced by this patch is listed below:
* dfl_fpga_port_ops_add
add one port ops to the global list.* dfl_fpga_port_ops_del
del one port ops from the global list.* dfl_fpga_port_ops_get / dfl_fpga_port_ops_put
get/put the port ops before/after use.Signed-off-by: Wu Hao
Acked-by: Alan Tull
Signed-off-by: Greg Kroah-Hartman
