Eric Lee / smarc-fsl-linux-kernel

08 Feb, 2013

1 commit

  • a0d2642e9   spi/pxa2xx: add support for Intel Low Power Subsystem SPI ... Browse Code »

    Intel LPSS SPI is pretty much the same as the PXA27xx SPI except that it
    has few additional features over the original:

    o FIFO depth is 256 entries
    o RX FIFO has one watermark
    o TX FIFO has two watermarks, low and high
    o chip select can be controlled by writing to a register

    The new FIFO registers follow immediately the PXA27xx registers but then there
    are some additional LPSS private registers at offset 1k or 2k from the base
    address. For these private registers we add new accessors that take advantage
    of drv_data->lpss_base once it is resolved.

    We add a new type LPSS_SSP that can be used to distinguish the LPSS devices
    from others.

    Signed-off-by: Mika Westerberg
    Tested-by: Lu Cao
    Signed-off-by: Mark Brown

    Mika Westerberg
     

08 Jan, 2013

1 commit

  • 851bacf59   spi/pxa2xx: embed the ssp_device to platform data ... Browse Code »

    The spi-pxa2xx-pci glue driver had to implement pxa_ssp_request()/free() in
    order to support the spi-pxa2xx platform driver. Since the ACPI enabled
    platforms can use the same platform driver we would need to implement
    pxa_ssp_request()/free() in some central place that can be shared by the
    ACPI and PCI glue code.

    Instead of doing that we can make pxa_ssp_request()/free() to be available
    only when CONFIG_ARCH_PXA is set. On other arches these are being stubbed
    out in preference to passing the ssp_device from the platform data
    directly.

    We also change the SPI bus number to be taken from ssp->port_id instead of
    platform device id. This way the supporting code that passes the ssp can
    decide the number (or it can set it to the same as pdev->id).

    Signed-off-by: Mika Westerberg
    Signed-off-by: Mark Brown

    Mika Westerberg
     

11 Jun, 2012

2 commits

31 Mar, 2011

1 commit

03 Dec, 2010

1 commit

  • 2a8626a9e   spi/pxa2xx: Add chipselect support for Sodaville ... Browse Code »

    The SPI core on Sodaville supports chip selects. Its configuration
    moved into the SSSR register at bit 0 and 1. Thus Sodaville can be hooked
    up with up to 4 devices.
    This patch ensures that the bits which are otherwiese reserved are only
    touched on Sodaville and not on any other PXAs. Also it makes sure that
    the status register does not lose the CS information while clearing the
    ROR bit.

    Signed-off-by: Sebastian Andrzej Siewior
    Signed-off-by: Dirk Brandewie

    Sebastian Andrzej Siewior
     

01 Dec, 2010

2 commits

  • d0777f2c3   spi/pxa2xx: Consider CE4100's FIFO depth ... Browse Code »

    For PXA the default threshold is FIFO_DEPTH / 2. Adjust this value for
    CE4100.

    Signed-off-by: Sebastian Andrzej Siewior
    Signed-off-by: Dirk Brandewie

    Sebastian Andrzej Siewior
     
  • 8348c259d   arm/pxa2xx: reorgazine SSP and SPI header files ... Browse Code »

    The PXA-SPI driver relies on some files / defines which are arm specific
    and are within the ARM tree. The CE4100 SoC which is x86 has also the
    SPI core.
    This patch moves the ssp and spi files from arm/mach-pxa and plat-pxa to
    include/linux where the CE4100 can access them.

    This move got verified by building the following defconfigs:
    cm_x2xx_defconfig corgi_defconfig em_x270_defconfig ezx_defconfig
    imote2_defconfig pxa3xx_defconfig spitz_defconfig zeus_defconfig
    raumfeld_defconfig magician_defconfig

    Signed-off-by: Sebastian Andrzej Siewior
    Signed-off-by: Dirk Brandewie

    Sebastian Andrzej Siewior