15 May, 2020
16 commits
-
We need to accumulate the input data length for calculating the
output length because there are data need to be prefilled in
the beginning. If the fraction part beyond the integrity of
sample is not considered in calculating, which may cause the
output task timeout.Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman -
Since iMX6Q/DL PCIe have the PM limitation (ERR005723).
Only enable PCIe in the xxx-pcie.dts files.Signed-off-by: Richard Zhu
Reviewed-by: Fugang Duan
(cherry picked from commit e07881a460c9afbaf5b56ccbd3ac27cfdc645b3f) -
Use "fsl,imx8mm-spdif" compat for SPDIF nodes.
Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang
(cherry picked from commit aeffa77173e66429254e85df6c2100f40e2436de) -
Add intermediate RX rates for iMX8MM.
Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang
(cherry picked from commit a4f24900c310f44af4f3399129476c3d231b74ba) -
Move the controller enablement from atomic plane update to
the CRTC's atomic enable, since some bridge(e.g. IT6263)
requires data stream from CRTC to be ready for its config.But this controller enablement change won't cause any side
effect, since the CRTC enable and plane update can be done
in one frame interval and to next frame all configurations
can take effect, which has the same behavior as before.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
(cherry picked from commit ea4f7e2d01e9dde69a34a3e2f0a4d194f60080d2) -
After the atomic plane update, the shadow load should be
enabled to make sure its update can take effect on next
frame in any cases. And this enable is better to be done
in CRTC's atomic_flush() which is called after plane's
atomic_update() is called.Besides, the shadow load enable in controller enable is
unnecessary, so remove it.Signed-off-by: Fancy Fang
Reviewed-by: Liu Ying
(cherry picked from commit bfa7236c8477e8993f074a3068ddc64c1614db06) -
When firmware exception, send error event instead of eos event,
avoid doubt or might send eos event twice(exception + parsed eos data).Signed-off-by: Shijie Qin
Reviewed-by: ming_qian
(cherry picked from commit 2f97227dd635efa0c6ea965ab2d9f7fc9bafe9fb) -
At SPDIF TX interrupt the firmware running on M0+ core
overwrites TX DPATH BYPASS FEM bit which turns the
expected PHY DMAC TX PLL clock 2*bitclock instead of
expected 10*bitclock if SAI PLL is used as PHY DMAC TX
PLL.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang
(cherry picked from commit ae30f694dad4fcbcba09e895505211f29d0a83ae) -
The existing "shutdown" callback does not consider
full duplex mode, fix this.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang
(cherry picked from commit 16346350984e9f613f8ef5945b14c4ce7c0d6e65) -
fix clk use-after-free issue
Signed-off-by: Zhou Peng
(cherry picked from commit 0d1b3814c976cb2148958f48c4c4f4701ced6b4e) -
release clk to avoid memory leak
Signed-off-by: Zhou Peng
(cherry picked from commit 420a357a1b43c57383c74a548a9a3714b6da7de2) -
release clk to avoid memory leak
Signed-off-by: Zhou Peng
(cherry picked from commit 76d95bf26376a7f774f2939052e3595b8d2aefdb) -
change module device table name to fix build error as module
rename the c source name to avoid conflict with h1
release clk avoid memory leak
fix typo error in core indexSigned-off-by: Zhou Peng
(cherry picked from commit 099a3ae272672978b7720257f012dcf38e537dc0) -
Combine pvi and pai power up/down functions to pavi_powerup/down
function. Move clock enable/disable function to power function.Signed-off-by: Sandor Yu
-
remove the redundant pm_runtime_get_sync introduced in last code rebase
Signed-off-by: Han Xu
(cherry picked from commit 529d3dc133ad98f56f97a1f95880959943ff6084) -
To get better performance, current gpmi driver collected and chained all
small DMA transfers in gpmi_nfc_exec_op, the whole chain triggered and
wait for complete at the end.But some random DMA timeout found in this new driver, with the help of
ftrace, we found the root cause is as follows:Take gpmi_ecc_read_page() as an example, gpmi_nfc_exec_op collected 6
DMA transfers and the DMA chain triggered at the end. It waits for bch
completion and check jiffies if it's timeout. The typical function graph
shown below,63.216351 | 1) | gpmi_ecc_read_page() {
63.216352 | 1) 0.750 us | gpmi_bch_layout_std();
63.216354 | 1) | gpmi_nfc_exec_op() {
63.216355 | 1) | gpmi_chain_command() {
63.216356 | 1) | mxs_dma_prep_slave_sg() {
63.216357 | 1) | /* mxs chan ccw idx: 0 */
63.216358 | 1) 1.750 us | }
63.216359 | 1) | mxs_dma_prep_slave_sg() {
63.216360 | 1) | /* mxs chan ccw idx: 1 */
63.216361 | 1) 2.000 us | }
63.216361 | 1) 6.500 us | }
63.216362 | 1) | gpmi_chain_command() {
63.216363 | 1) | mxs_dma_prep_slave_sg() {
63.216364 | 1) | /* mxs chan ccw idx: 2 */
63.216365 | 1) 1.750 us | }
63.216366 | 1) | mxs_dma_prep_slave_sg() {
63.216367 | 1) | /* mxs chan ccw idx: 3 */
63.216367 | 1) 1.750 us | }
63.216368 | 1) 5.875 us | }
63.216369 | 1) | /* gpmi_chain_wait_ready */
63.216370 | 1) | mxs_dma_prep_slave_sg() {
63.216372 | 1) | /* mxs chan ccw idx: 4 */
63.216373 | 1) 3.000 us | }
63.216374 | 1) | /* gpmi_chain_data_read */
63.216376 | 1) | mxs_dma_prep_slave_sg() {
63.216377 | 1) | /* mxs chan ccw idx: 5 */
63.216378 | 1) 2.000 us | }
63.216379 | 1) 1.125 us | mxs_dma_tx_submit();
63.216381 | 1) 1.000 us | mxs_dma_enable_chan();
63.216712 | 0) 2.625 us | mxs_dma_int_handler();
63.216717 | 0) 4.250 us | bch_irq();
63.216723 | 0) 1.250 us | mxs_dma_tasklet();
63.216723 | 1) | /* jiffies left 250 */
63.216725 | 1) ! 372.000 us | }
63.216726 | 1) 2.625 us | gpmi_count_bitflips();
63.216730 | 1) ! 379.125 us | }but it's not gurantee that bch irq handled always after dma irq handled,
sometimes bch_irq comes first and gpmi_nfc_exec_op won't wait anymore,
another gpmi_nfc_exec_op may get invoked before last DMA chain IRQ
handled, this messed up the next DMA chain and causes DMA timeout. Check
the trace log when issue happened.63.218923 | 1) | gpmi_ecc_read_page() {
63.218924 | 1) 0.625 us | gpmi_bch_layout_std();
63.218926 | 1) | gpmi_nfc_exec_op() {
63.218927 | 1) | gpmi_chain_command() {
63.218928 | 1) | mxs_dma_prep_slave_sg() {
63.218929 | 1) | /* mxs chan ccw idx: 0 */
63.218929 | 1) 1.625 us | }
63.218931 | 1) | mxs_dma_prep_slave_sg() {
63.218931 | 1) | /* mxs chan ccw idx: 1 */
63.218932 | 1) 1.750 us | }
63.218933 | 1) 5.875 us | }
63.218934 | 1) | gpmi_chain_command() {
63.218934 | 1) | mxs_dma_prep_slave_sg() {
63.218935 | 1) | /* mxs chan ccw idx: 2 */
63.218936 | 1) 1.875 us | }
63.218937 | 1) | mxs_dma_prep_slave_sg() {
63.218938 | 1) | /* mxs chan ccw idx: 3 */
63.218939 | 1) 1.625 us | }
63.218939 | 1) 5.875 us | }
63.218940 | 1) | /* gpmi_chain_wait_ready */
63.218941 | 1) | mxs_dma_prep_slave_sg() {
63.218942 | 1) | /* mxs chan ccw idx: 4 */
63.218942 | 1) 1.625 us | }
63.218943 | 1) | /* gpmi_chain_data_read */
63.218944 | 1) | mxs_dma_prep_slave_sg() {
63.218945 | 1) | /* mxs chan ccw idx: 5 */
63.218947 | 1) 2.375 us | }
63.218948 | 1) 0.625 us | mxs_dma_tx_submit();
63.218949 | 1) 1.000 us | mxs_dma_enable_chan();
63.219276 | 0) 5.125 us | bch_irq();
(cherry picked from commit 5dde5bcfd7fab7a6cb9974b79f7d36cbf64b85fb)
14 May, 2020
2 commits
-
- Don't limit to only PCIe GEN1 when do the compliance tests.
- Configure the TX drive level of iMX865 PHY, adjust the peak output
voltage to pass the PCIe GEN1 compliance tests.Signed-off-by: Richard Zhu
Reviewed-by: Frank Li
(cherry picked from commit af235be4424b003b2adc53c39f57f8ed00b0e342) -
The current DT file for the i.MX8x MEK platform has a pin conflict for
IMX8QXP_SPI0_CS1 bewteen the sai1 node and the adma_pwm node(as needed
by the parallel display panel backlight control). This patch enables
the adma_pwm node in display specific DT file to avoid the conflict.
Also, the lcdif_backlight is moved to display specific as it is
referencing the adma_pwm node.Fixes: 62408b1461b6 ("LF-1189-13 arm64: dts: imx8qxp-mek: Add adma_pwm support")
Signed-off-by: Liu Ying
Reviewed-by: Shengjiu Wang
Reviewed-by: Daniel Baluta
(cherry picked from commit 0735da29ed030b5449e3aaf22ddca7df1fabc8df)
13 May, 2020
11 commits
-
Enable generic SW crypto algorithms needed for tcrypt speed tests
Signed-off-by: Dragos Rosioru
-
Enable generic SW crypto algorithms needed for tcrypt speed tests
Signed-off-by: Dragos Rosioru
-
Increase the PAD drive strength for usdhc2 to avoid cmd53 error.
Reviewed-by: Haibo Chen
Signed-off-by: Fugang Duan -
Fix below build warning:
warning: format ‘%li’ expects argument of type ‘long int’, but argument 3 has type ‘unsigned int’ [-Wformat=]
"Exceed max msg size (%li) on TX, got: %i\n",Reviewed-by: Ye Li
Signed-off-by: Peng Fan
(cherry picked from commit 6566c7b54aef56d7a4bf83f75615c7c4d39f98ad) -
iMX8MN DDR4 and LPDDR4 SOM on Audio Board 2.0
enable base support, ADC and SPDIF.Reviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from commit 9b0f536b2d89a2e2463c0ce80d7f5f4209299c39) -
iMX8MM LPDDR4 SOM on Audio Board 2.0 enable base support
SPDIF, ADC and dual DACReviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from commit e472912f9fdc03d60d04e5cd35b61c6664a77a02) -
Add missing sai mclk0 dummy clk expected by SAI
driver, fix error:
fsl-sai 30020000.sai: failed to get mclk0 clock: -2Reviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from commit abf5f0311a3ec7f03ec8ebc3c263db5522fa7f3d) -
imx8mm EVK 8mic Rev E PDM to PCM software
decimation support MIC capture on SAI5Reviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from commit a40a3becc8c50f397d52a6918ad8b935ccfc5332) -
Add support for 8mic rev E PDM mic array board
support for gpio leds and software keys events:SW1: KEY_F9 Factory reset for Android
SW2: VOLUME_MUTE
SW3: VOLUME_UP
SW4: VOLUME_DOWNReviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from commit 225ecf99571a2fec936add9547f53206404611da) -
Update drivers constrains, limit sample rates to
[8Khz - 64Khz] and up to 8 channels.
Use SND_SOC_DAIFMT_PDM format type and remove
tdm slot settings to allow capture from multiple
SAI_RxD pins.Reviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from commit c9f12b9c9e60d93ce011a6d37ebceb78ac910300) -
Add missing vcc-supply assing buck4_reg which corresponds
to VDD_3V3 from pmic, fixes probe pca6416 driverReviewed-by: Shengjiu Wang
Signed-off-by: Adrian Alonso
(cherry picked from 6320b2a01eb5f6f1f20059fe5da2799bd5ba9f6a)
12 May, 2020
11 commits
-
The criteria used to drop eARC mode into ARC mode
makes eARC function to fail. Drop it for now.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang -
Lower power audio needs the audiomix power domain be enabled when running
For the resource in audiomix is used by M7 core.Signed-off-by: Shengjiu Wang
Reviewed-by: Viorel Suman -
When the nvmem subsystem is not initialised at boot, the probe
will fail and an error message will be displayed.
In this case the message should not be printed as the driver will
be probed later.This patch checks the error code from nvmem before printing the
message.It also fixes the cleaning path as the driver was not exiting
properly.Signed-off-by: Franck LENORMAND
Reviewed-by: Iuliana Prodan -
It is better to re-init request list for EP0 when the EP0 begins to
uses.Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
The new usb_gadget_disconnect API includes both calling class
driver's disconnect and calling .pullup at udc driver, so we
could simply your udc driver handling.Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
We do not want to handle any interrupts after usb_gadget_disconnect
is called.Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
Below is the recommendation from Cadence designer:
Using this bit to be sure that PHY clock is keeping up in active
state. It's good to keep Fast Access bit enabled as long as there
is any access to USB register.It is used to fix the potential ARM core hang when visit controller
register after DEVDS is set.Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
And there are no multiple TRBs on EP0 and WA1 workaround,
so it doesn't need to change TRB for EP0. It fixes below oops.configfs-gadget gadget: high-speed config #1: b
android_work: sent uevent USB_STATE=CONFIGURED
Unable to handle kernel read from unreadable memory at virtual address 0000000000000008
Mem abort info:
android_work: sent uevent USB_STATE=DISCONNECTED
ESR = 0x96000004
EC = 0x25: DABT (current EL), IL = 32 bitsSET = 0, FnV = 0
EA = 0, S1PTW = 0
Data abort info:
ISV = 0, ISS = 0x00000004
CM = 0, WnR = 0
user pgtable: 4k pages, 48-bit VAs, pgdp=00000008b5bb7000
[0000000000000008] pgd=0000000000000000
Internal error: Oops: 96000004 [#1] PREEMPT SMP
Modules linked in:
CPU: 2 PID: 430 Comm: HwBinder:401_1 Not tainted 5.4.24-06071-g6fa8921409c1-dirty #77
Hardware name: Freescale i.MX8QXP MEK (DT)
pstate: 60400085 (nZCv daIf +PAN -UAO)
pc : cdns3_gadget_ep_dequeue+0x1d4/0x270
lr : cdns3_gadget_ep_dequeue+0x48/0x270
sp : ffff800012763ba0
x29: ffff800012763ba0 x28: ffff00082c653c00
x27: 0000000000000000 x26: ffff000068fa7b00
x25: ffff0000699b2000 x24: ffff00082c6ac000
x23: ffff000834f0a480 x22: ffff000834e87b9c
x21: 0000000000000000 x20: ffff000834e87800
x19: ffff000069eddc00 x18: 0000000000000000
x17: 0000000000000000 x16: 0000000000000000
x15: 0000000000000000 x14: 0000000000000000
x13: 0000000000000000 x12: 0000000000000001
x11: ffff80001180fbe8 x10: 0000000000000001
x9 : ffff800012101558 x8 : 0000000000000001
x7 : 0000000000000006 x6 : ffff000835d9c668
x5 : ffff000834f0a4c8 x4 : 0000000096000000
x3 : 0000000000001810 x2 : 0000000000000000
x1 : ffff800024bd001c x0 : 0000000000000001
Call trace:
cdns3_gadget_ep_dequeue+0x1d4/0x270
usb_ep_dequeue+0x34/0xf8
composite_dev_cleanup+0x154/0x170
configfs_composite_unbind+0x6c/0xa8
usb_gadget_remove_driver+0x44/0x70
usb_gadget_unregister_driver+0x74/0xe0
unregister_gadget+0x28/0x58
gadget_dev_desc_UDC_store+0x80/0x110
configfs_write_file+0x1e0/0x2a0
__vfs_write+0x48/0x90
vfs_write+0xe4/0x1c8
ksys_write+0x78/0x100
__arm64_sys_write+0x24/0x30
el0_svc_common.constprop.0+0x74/0x168
el0_svc_handler+0x34/0xa0
el0_svc+0x8/0xc
Code: 52830203 b9407660 f94042e4 11000400 (b9400841)
---[ end trace 1574516e4c1772ca ]---
Kernel panic - not syncing: Fatal exception
SMP: stopping secondary CPUs
Kernel Offset: disabled
CPU features: 0x0002,20002008
Memory Limit: none
Rebooting in 5 seconds..Fixes: f616c3bda47e ("usb: cdns3: Fix dequeue implementation")
Cc: stable
Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
Assign interrupt number to USB gadget structure.
Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
The threaded interrupt handler may still be called after the
usb_gadget_disconnect is called, it causes the structures used
at interrupt handler was freed before it uses, eg the
usb_request. This issue usually occurs we remove the udc function
during the transfer. Below is the example when doing stress
test for android switch function, the EP0's request is freed
by .unbind (configfs_composite_unbind -> composite_dev_cleanup),
but the threaded handler accesses this request during handling
setup packet request.In fact, there is no protection between unbind the udc
and udc interrupt handling, so we have to avoid the interrupt
handler is occurred or scheduled during the .unbind flow.init: Sending signal 9 to service 'adbd' (pid 18077) process group...
android_work: did not send uevent (0 0 000000007bec2039)
libprocessgroup: Successfully killed process cgroup uid 0 pid 18077 in 6ms
init: Service 'adbd' (pid 18077) received signal 9
init: Sending signal 9 to service 'adbd' (pid 18077) process group...
libprocessgroup: Successfully killed process cgroup uid 0 pid 18077 in 0ms
init: processing action (init.svc.adbd=stopped) from (/init.usb.configfs.rc:14)
init: Received control message 'start' for 'adbd' from pid: 399 (/vendor/bin/hw/android.hardware.usb@1.init: starting service 'adbd'...
read descriptors
read strings
Unable to handle kernel read from unreadable memory at virtual address 000000000000002a
android_work: sent uevent USB_STATE=CONNECTED
Mem abort info:
ESR = 0x96000004
EC = 0x25: DABT (current EL), IL = 32 bits
SET = 0, FnV = 0
EA = 0, S1PTW = 0
Data abort info:
ISV = 0, ISS = 0x00000004
CM = 0, WnR = 0
user pgtable: 4k pages, 48-bit VAs, pgdp=00000000e97f1000
using random self ethernet address
[000000000000002a] pgd=0000000000000000
Internal error: Oops: 96000004 [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 232 Comm: irq/68-5b110000 Not tainted 5.4.24-06075-g94a6b52b5815 #92
Hardware name: Freescale i.MX8QXP MEK (DT)
pstate: 00400085 (nzcv daIf +PAN -UAO)
using random host ethernet address
pc : composite_setup+0x5c/0x1730
lr : android_setup+0xc0/0x148
sp : ffff80001349bba0
x29: ffff80001349bba0 x28: ffff00083a50da00
x27: ffff8000124e6000 x26: ffff800010177950
x25: 0000000000000040 x24: ffff000834e18010
x23: 0000000000000000 x22: 0000000000000000
x21: ffff00083a50da00 x20: ffff00082e75ec40
x19: 0000000000000000 x18: 0000000000000000
x17: 0000000000000000 x16: 0000000000000000
x15: 0000000000000000 x14: 0000000000000000
x13: 0000000000000000 x12: 0000000000000001
x11: ffff80001180fb58 x10: 0000000000000040
x9 : ffff8000120fc980 x8 : 0000000000000000
x7 : ffff00083f98df50 x6 : 0000000000000100
x5 : 00000307e8978431 x4 : ffff800011386788
x3 : 0000000000000000 x2 : ffff800012342000
x1 : 0000000000000000 x0 : ffff800010c6d3a0
Call trace:
composite_setup+0x5c/0x1730
android_setup+0xc0/0x148
cdns3_ep0_delegate_req+0x64/0x90
cdns3_check_ep0_interrupt_proceed+0x384/0x738
cdns3_device_thread_irq_handler+0x124/0x6e0
cdns3_thread_irq+0x94/0xa0
irq_thread_fn+0x30/0xa0
irq_thread+0x150/0x248
kthread+0xfc/0x128
ret_from_fork+0x10/0x18
Code: 910e8000 f9400693 12001ed7 79400f79 (3940aa61)
---[ end trace c685db37f8773fba ]---
Kernel panic - not syncing: Fatal exception
SMP: stopping secondary CPUs
Kernel Offset: disabled
CPU features: 0x0002,20002008
Memory Limit: none
Rebooting in 5 seconds..Reviewed-by: Jun Li
Signed-off-by: Peter Chen -
Make same change as i.mx8mp.
Signed-off-by: Robin Gong
Reviewed-by: Anson Huang
(cherry picked from commit f25b74f7853295798fb0a7c0f3e9e783f53f65f8)
