25 Sep, 2006
15 commits
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Split the iop3xx mach type into iop32x and iop33x -- split the config
symbols, and move the code in the mach-iop3xx directory to the mach-iop32x
and mach-iop33x directories.Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King -
Rename CONFIG_ARCH_IOP321 to CONFIG_ARCH_IOP32X and
CONFIG_ARCH_IOP331 to CONFIG_ARCH_IOP33X.Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King -
Clear both the EINT and INT status before
going to sleep, otherwise we may end up being
woken by something that was not set in our
wakeup map.Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
The s3c24xx_va_gpio2 variable is only used
when the S3C2412 and another cpu-type is
being used in the kernel. This patch ensures
it is not set when it is not being used.Fixes bug report by Thomas Gleixner.
Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
Remove the S3C2410 specific items out of the
core PM code. Add sysdev driver for all the
S3C24XX series that used the S3C2410 PM code.Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
DMA channel mappings for the S3C2312
Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
clear the dirty bits, which means that if we invalidate a dirty line,
the dirty data can still be written back to memory later on.To work around this, dma_inv_range() on these two processors is
implemented as dma_flush_range() (i.e. do a clean D-cache line before
doing the invalidate D-cache line.) For this, we currently have a
processor ID check in xscale_dma_inv_range(), but a better solution
is to add a separate cache_fns and proc_info for A0/A1 80200.Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King -
Prevent userland from mapping in physical address regions >= 4G by
checking for that in valid_mmap_phys_addr_range().Unfortunately, we cannot override valid_mmap_phys_addr_range() without
also overriding valid_phys_addr_range(), so copy drivers/char/mem.c's
version of valid_phys_addr_range() over to arch/arm/mm/mmap.c as well.Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King -
Add Cirrus Logic EDB9312 support.
Signed-off-by: Lennert Buytenhek
Signed-off-by: Russell King -
Change to using flush_cache_all() in pm.c and
also remove the need to flush the cache in the
PM code.This changes the sleep.S code to have an entry
to store the registers for resume, and then a
second entry (after the caches are cleaned)
to do the suspend and resume.Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
Seperate the IRQ power management code out of
the pm.c file, and add it to the relevant
system class devices.Also make the suspend and resume code take
notice of the fact these registers can be
moved by compile time code.Add fix from Ilya Yanok to also save the
INTSUBMSK over sleep.Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
DMA channel mappings for the S3C2442
Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
S3C2440 DMA channel mappings
Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
DMA channel mappings for the S3C2410
Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
Allow each CPU type in the S3C24XX range to
select the DMA channel mapping it supports.We change the DMA registration to use an
virtual channel number that the DMA system
will allocate to a hardware channel at
request time.Signed-off-by: Ben Dooks
Signed-off-by: Russell King
20 Sep, 2006
5 commits
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Patch from Daniel Jacobowitz
The ARM kernel has several uses of asm("foo%?"). %? is a GCC internal
modifier used to output conditional execution predicates. However, no
version of GCC supports conditionalizing asm statements. GCC 4.2 will
correctly expand %? to the empty string in user asms. Earlier versions may
reuse the condition from the previous instruction. In 'if (foo) asm
("bar%?");' this is somewhat likely to be right... but not reliable.So, the only safe thing to do is to remove the uses of %?. I believe
the tlbflush.h occurances were supposed to be removed before, based
on the comment about %? not working at the top of that file.Old versions of GCC could omit branches around user asms if the asm didn't
mark the condition codes as clobbered. This problem hasn't been seen on any
recent (3.x or 4.x) GCC, but it could theoretically happen. So, where
%? was removed a cc clobber was added.Signed-off-by: Daniel Jacobowitz
Signed-off-by: Russell King -
The common case for the thread notifier is a context switch. Tell
gcc that this is the most likely condition so it can optimise the
function for this case.Signed-off-by: Russell King
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This adds support for irqtrace for lockdep on ARM.
Signed-off-by: Russell King
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Rename mmu.c to context.c - it's the ARMv6 ASID context handling
code rather than generic "mmu" handling code.Signed-off-by: Russell King
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Move top_pmd into arch/arm/mm/mm.h - nothing outside arch/arm/mm
references it.Move the repeated definition of TOP_PTE into mm/mm.h, as well as
a few function prototypes.Signed-off-by: Russell King
19 Sep, 2006
4 commits
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This reverts commits 11012d419cfc0e0f78ca356aca03674217910124 and
40dd2d20f220eda1cd0da8ea3f0f9db8971ba237, which allowed us to use the
MMIO accesses for PCI config cycles even without the area being marked
reserved in the e820 memory tables.Those changes were needed for EFI-environment Intel macs, but broke some
newer Intel 965 boards, so for now it's better to revert to our old
2.6.17 behaviour and at least avoid introducing any new breakage.Andi Kleen has a set of patches that work with both EFI and the broken
Intel 965 boards, which will be applied once they get wider testing.Cc: Arjan van de Ven
Cc: Edgar Hucek
Cc: Andi Kleen
Signed-off-by: Linus Torvalds -
(And reset it on new thread creation)
It turns out that eflags is important to save and restore not just
because of iopl, but due to the magic bits like the NT bit, which we
don't want leaking between different threads.Tested-by: Mike Galbraith
Signed-off-by: Linus Torvalds -
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6:
[SPARC]: Fix regression in sys_getdomainname()
[OPENPROMIO]: Handle current_node being NULL correctly. -
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 3815/1: headers_install support for ARM
[ARM] 3794/1: S3C24XX: do not defined set_irq_wake when no CONFIG_PM
[ARM] 3793/1: S3C2412: fix wrong serial info struct
[ARM] 3780/1: Fix iop321 cpuid
[ARM] 3786/1: pnx4008: update defconfig
[ARM] 3785/1: S3C2412: Fix idle code as default uses wrong clocks
[ARM] 3784/1: S3C2413: fix config for MACH_S3C2413/MACH_SMDK2413
18 Sep, 2006
2 commits
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This patch corrects the buffer length checking in the
sys_getdomainname() implementation for sparc/sparc64.Signed-off-by: Andy Walker
Signed-off-by: David S. Miller -
Patch from Ben Dooks
Do not define set_irq_wake as a real function if
the CONFIG_PM option is not set.Fixes bug reported by Thomas Gleixner.
Signed-off-by: Ben Dooks
Signed-off-by: Russell King
17 Sep, 2006
1 commit
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Add the CPU identification needed by oprofile for Intel (r) Core (tm) 2
CPUs.Signed-off-by: Benjamin LaHaise
Signed-off-by: Andi Kleen
Cc: "Arun Sharma"
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
15 Sep, 2006
1 commit
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Patch from Dan Williams
commit a6a38a66224c7c578cfed2f584b440c81af0c3ae changed the iop321 id to a value that does not work with all platforms. Change the mask to permit bit 11. Tested on an iq80321 600Mhz CRB.
Signed-off-by: Dan Williams
Signed-off-by: Russell King
14 Sep, 2006
3 commits
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Patch from Vitaly Wool
This patch updates the default configuration file for PNX4008.
arch/arm/configs/pnx4008_defconfig | 715 +++++++------------------------------
1 file changed, 154 insertions(+), 561 deletions(-)Signed-off-by: Vitaly Wool
Signed-off-by: Russell King -
Patch from Ben Dooks
Fix the idle code on the s3c2412 as the default
code is using bits in the CLKCON register that are
no-longer there.Provide an override for the idle code, and ensure
that the power configuration is set to allow idle
instead of stop or sleep.Signed-off-by: Ben Dooks
Signed-off-by: Russell King -
Patch from Ben Dooks
These two machines are identical, and supported
by the SMDK2413 configuration. When MACH_SMDK2413
is selected, we must also select MACH_S3C2413
to allow machine_is_smdk2413() or machine_is_s3c2413()
to work.Signed-off-by: Ben Dooks
Signed-off-by: Russell King
13 Sep, 2006
7 commits
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* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
[POWERPC] Fix G5 DART (IOMMU) race causing occasional data corruption
[POWERPC] Fix MMIO ops to provide expected barrier behaviour
[POWERPC] Fix interrupt clearing in kdump shutdown sequence
[POWERPC] update prep_defconfig
[POWERPC] kdump: Support kernels having 64k page size.
[POWERPC] Implement PowerPC futex_atomic_cmpxchg_inatomic().
[POWERPC] Add new, missing argument to of_irq_map_raw() for 86xx.
[POWERPC] Update defconfigs -
It seems that the occasional data corruption observed with the tg3
driver wasn't due to missing barriers after all, but rather seems to
be due to the DART (= IOMMU) in the U4 northbridge reading stale
IOMMU table entries from memory due to a race. This fixes it by
making the CPU read the entry back from memory before using it.Signed-off-by: Benjamin Herrenschmidt
Signed-off-by: Paul Mackerras -
This changes the writeX family of functions to have a sync instruction
before the MMIO store rather than after, because the generally expected
behaviour is that the device receiving the MMIO store can be guaranteed
to see the effects of any preceding writes to normal memory.To preserve ordering between writeX and readX, and to preserve ordering
between preceding stores and the readX, the readX family of functions
have had an sync added before the load.Although writeX followed by spin_unlock is not officially guaranteed
to keep the writeX inside the spin-locked region unless an mmiowb()
is used, there are currently drivers that depend on the previous
behaviour on powerpc, which was that the mmiowb wasn't actually required.
Therefore we have a per-cpu flag that is set by writeX, cleared by
__raw_spin_lock and mmiowb, and tested by __raw_spin_unlock. If it is
set, __raw_spin_unlock does a sync and clears it.This changes both 32-bit and 64-bit readX/writeX. 32-bit already has a
sync in __raw_spin_unlock (since lwsync doesn't exist on 32-bit), and thus
doesn't need the per-cpu flag.Tested on G5 (PPC970) and POWER5.
Signed-off-by: Paul Mackerras
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Call chip->eoi(irq) to clear any pending interrupt in case of kdump
shutdown sequence. chip->end(irq) does not serve this purpose.Signed-off-by: Mohan Kumar M
Signed-off-by: Paul Mackerras -
Update PReP defconfig, disable some drivers for hardware that is not
used on those systems; enable SL82C105 IDE driver for Powerstack.Signed-off-by: Olaf Hering
Signed-off-by: Paul Mackerras -
Ben speaks; we follow.
Signed-off-by: Jon Loeliger
Signed-off-by: Paul Mackerras -
* 'audit.b29' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/audit-current:
[PATCH] sparc64 audit syscall classes hookup
[PATCH] syscall class hookup for all normal targets
12 Sep, 2006
2 commits
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... that should do it for all targets; the only remaining issues are
mips (currently treated as non-biarch) and handling of other OS
emulations (OSF/SunOS/Solaris/???). The latter would need to be
assigned new AUDIT_ARCH_... ABI numbers anyway...Signed-off-by: Al Viro
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Take default arch/*/kernel/audit.c to lib/, have those with special
needs (== biarch) define AUDIT_ARCH in their Kconfig.Signed-off-by: Al Viro
