16 Aug, 2007
4 commits
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Signed-off-by: David S. Miller
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This register is not a part of the sun4v architecture.
Niagara 1 and 2 happened to leave it around.
Signed-off-by: David S. Miller
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The bzero/memset implementation stays the same as Niagara-1.
Signed-off-by: David S. Miller
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Like the OF device tree, it's useful to let userland get
at the machine description so it can pretty print the
graph etc.The implementation is a simple MISC device with a read method.
Signed-off-by: David S. Miller
15 Aug, 2007
2 commits
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In sun4c_init_clean_mmu(), aligning 'kernel_end' using
SUN4C_REAL_PGDIR_ALIGN() is unnecessary since the caller
does this already.In sun4c_paging_init(), 4 page sizes of "fluff" were added
to the address of &end. This was necessary a long time ago
when sparc32 would allocate some early data structures
by carving out memory chunks after &end but that no longer
occurs.Signed-off-by: Mark Fortescue
Signed-off-by: David S. Miller -
This mirrors sparc64 commit 715a0ecc29c850d2b2f76e1803d3f22cd5a0ac0d
sparc_ramdisk_image should always be decremented by KERNBASE.
Signed-off-by: Mark Fortescue
Signed-off-by: David S. Miller
11 Aug, 2007
1 commit
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Signed-off-by: Robert Reif
Signed-off-by: David S. Miller
09 Aug, 2007
2 commits
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Every time a cpu is added via hotplug, we allocate the per-cpu MONDO
queues but we never free them up. Freeing isn't easy since the first
cpu gets this memory from bootmem.Therefore, the simplest thing to do to fix this bug is to allocate the
queues for all possible cpus at boot time.Signed-off-by: David S. Miller
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Check the cpu type in the OBP device tree before committing to
using the optimized Niagara memcpy and memset implementation.If we don't recognize the cpu type, use a completely generic
version.Signed-off-by: David S. Miller
08 Aug, 2007
2 commits
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Signed-off-by: David S. Miller
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Signed-off-by: David S. Miller
06 Aug, 2007
1 commit
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Signed-off-by: Russell King
05 Aug, 2007
2 commits
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- Include atmel_lcdc.h in at91sam926{1,3}_devices.c
Signed-off-by: Jan Altenberg
Signed-off-by: Russell King -
With the availability of the iop-adma driver iop platforms can now use
their offload engines for md-raid5 (copy+xor) and net-dma (tcp receive
copy) offload.Cc: Lennert Buytenhek
Signed-off-by: Dan Williams
Signed-off-by: Russell King
04 Aug, 2007
3 commits
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* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc:
[POWERPC] Fixes for the SLB shadow buffer code
[POWERPC] Fix a compile warning in powermac/feature.c
[POWERPC] Fix a compile warning in pci_32.c
[POWERPC] Fix parse_drconf_memory() for 64-bit start addresses
[POWERPC] Fix num_cpus calculation in smp_call_function_map()
[POWERPC] ps3: Fix section mismatch in ps3/setup.c
[POWERPC] spufs: Fix affinity after introduction of node_allowed() calls
[POWERPC] Fix special PTE code for secondary hash bucket
[POWERPC] Expand RPN field to 34 bits when using 64k pages -
* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6.23:
sh: fix defconfigs for sh7751r boards
sh: fix cf support on r2d boards
sh: update r2d defconfig
sh: update snapgear defconfig.
sh: Fix SH-X3 FPU exception handling.
sh: Fix pgd mismatch from cached TTB in unhandled fault.
sh: Don't include fault-nommu on SH-2/SH-2A.
sh: Fix irqflags tracing for SH-3/4 nommu.
sh: Fix lockdep debugging oops on SH-3/4. -
Signed-off-by: David S. Miller
03 Aug, 2007
13 commits
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On a machine with hardware 64kB pages and a kernel configured for a
64kB base page size, we need to change the vmalloc segment from 64kB
pages to 4kB pages if some driver creates a non-cacheable mapping in
the vmalloc area. However, we never updated with SLB shadow buffer.
This fixes it. Thanks to paulus for finding this.Also added some write barriers to ensure the shadow buffer contents
are always consistent.Signed-off-by: Michael Neuling
Signed-off-by: Paul Mackerras -
...by using the pci_get API instead of the deprecated old stuff.
Signed-off-by: Segher Boessenkool
Signed-off-by: Paul Mackerras -
__must_check, so do so.
Signed-off-by: Segher Boessenkool
Signed-off-by: Paul Mackerras -
Some new machines use the "ibm,dynamic-reconfiguration-memory" property
to provide memory layout information, rather than via memory nodes.There is a bug in the code to parse this property for start addresses
over 4GB; we store the start address in an unsigned int, which means
we throw away the high bits and add apparently duplicate regions.
This results in a BUG() in free_bootmem_core(). This fixes it by
using an unsigned long instead.Signed-off-by: Michael Ellerman
Signed-off-by: Paul Mackerras -
In smp_call_function_map(), num_cpus is set to the number of online
CPUs minus one. However, if the CPU mask does not include all CPUs
(except the one we're running on), the routine will hang in the first
while() loop until the 8 second timeout occurs.The num_cpus should be set to the number of CPUs specified in the mask
passed into the routine, after we've made any modifications to the
mask. With this change, we can also get rid of the call to
cpus_empty() and avoid adding another pass through the bitmask.Signed-off-by: Kevin Corry
Signed-off-by: Carl Love
Signed-off-by: Paul Mackerras -
WARNING: vmlinux.o(.text+0x605d4): Section mismatch: reference to
.init.text:.__alloc_bootmem (between '.prealloc' and '.ps3_power_save')Signed-off-by: Stephen Rothwell
Signed-off-by: Paul Mackerras -
This patch fixes affinity reference point placement, which was not being
done in some situations, after the introduction of node_allowed() calls.The previously used parameter, 'ctx', is just the iterator of the
previous list_for_each_entry_reverse loop, and its value might be
invalid at the end of the loop. Also, the right context to seek
for information when defining the reference ctx location
_is_ the reference ctx.Signed-off-by: Andre Detsch
Signed-off-by: Arnd Bergmann
Signed-off-by: Jeremy Kerr
Signed-off-by: Paul Mackerras -
The code for mapping special 4k pages on kernels using a 64kB base
page size was missing the code for doing the RPN (real page number)
manipulation when inserting the hardware PTE in the secondary hash
bucket. It needs the same code as has already been added to the
code that inserts the HPTE in the primary hash bucket. This adds it.Spotted by Ben Herrenschmidt.
Signed-off-by: Paul Mackerras
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This patch fixes up the defconfig for various sh7751r based boards
by updating them to the single cpu subtype CONFIG_CPU_SUBTYPE_SH7751R.
The following sh4 boards are updated: hs7751rvoip, landisk, lboxre2,
systemh, titan.The current defconfigs with two subtypes defined trigger a configuration
bug which result in kernel configurations with missing board support
code. We end up with kernels without board code and with generic machvec
only.So we need this patch to make sure the board code gets compiled in.
Signed-off-by: Magnus Damm
Signed-off-by: Paul Mundt -
This patch makes sure cf support is enabled on R2D-PLUS but disabled
on R2D-1. Without this fix R2D-1 boards hang on bootup.Signed-off-by: Magnus Damm
Signed-off-by: Paul Mundt -
- Disable CONFIG_SH_DMA to avoid boot up freeze on R2D-1
- Disable CONFIG_SH_STANDARD_BIOS to support R2D-PLUS boot loadersSigned-off-by: Magnus Damm
Signed-off-by: Paul Mundt -
Updated the snapgear defconfig to get a booting kernel.
Signed-off-by: David McCullough
Signed-off-by: Paul Mundt -
Add a missing =m constraint to the EDD-probing code, that could have
caused improper dead-code elimination.Signed-off-by: H. Peter Anvin
02 Aug, 2007
6 commits
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Add memory operand constraint and write-only modifier to the inline
assembly to effect the writing of the EDID block to boot_params.edid_info.Without this, gcc would think the EDID query was dead code and would
eliminate it.Signed-off-by: Antonino Daplas
Signed-off-by: H. Peter Anvin -
* 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6:
[IA64] ITC: Reduce rating for ITC clock if ITCs are drifty
[IA64] SN2: Fix up sn2_rtc clock
[IA64] Fix wrong access to irq_desc[] in iosapic_register_intr().
[IA64] Fix possible race in destroy_and_reserve_irq()
[IA64] Fix registered interrupt check
[IA64] Remove a few duplicate includes
[IA64] Allow smp_call_function_single() to current cpu
[IA64] fix a few section mismatch warnings -
Enable the MB93090 motherboard's MB86943 PCI arbiter correctly by assigning to
the register rather than comparing against it. This is required to support
bus mastering.Signed-off-by: David Howells
Signed-off-by: Linus Torvalds -
Make sure to reduce the rating of the ITC clock if ITCs are drifty. If they
are drifting then we have not synchronized the ITC values, nor are we doing
the jitter compensation (useless since drift may increase the differentials
arbitrarily).Without this patch it is possible that the ITC clock becomes selected as
the system clock on systems with drifty ITCs which will result in
nanosleep hanging.One can still select the itc clock manually on such systems via
clocksource=itc
(Produces nice hangs on SGI Altix.)
Signed-off-by: Christoph Lameter
Signed-off-by: Tony Luck -
If the sn2_rtc clock is present then it is a must have since sn2_rtc
provides a synchronized time source on Altix systems. So elevate
the priority to 450. Otherwise the ITC would take precendence. Altix
systems currently do not boot because the ITC clocksource is broken. It
seems to assume that ITCs are synchronized and as a result nanosleep
hangs (may be fixed in a different patch).While we are at it: Remove the sn2_mc definition. The sn2_rtc has a fixed
address. No point in reading the address from memory. Removing it avoids
touching one cacheline.Signed-off-by: Christoph Lameter
Signed-off-by: Tony Luck -
In error path we must unlock irq_desc[irq].lock before we change
'irq'.Signed-off-by: Kenji Kaneshige
Signed-off-by: Tony Luck
01 Aug, 2007
4 commits
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SH-X3 has the FPU exceptions on different vectors completely,
patch in do_fpu_state_restore() to the proper vectors.Results in a much happier userspace.
Signed-off-by: Paul Mundt
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When reading the cached TTB value and extracting the pgd, we
accidentally applied a __va() to it and bumped it off in to bogus
space which ended up causing multiple faults in the error path.Fix it up so unhandled faults don't do strange and highly unorthodox
things when oopsing.Signed-off-by: Paul Mundt
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fault-nommu defines the page fault handler stubs for SH-3/4 parts,
but is not needed on SH-2/SH-2A now that the entry code has been
logically separated.Add it in for SH-3 and SH-4 explicitly.
Signed-off-by: Paul Mundt
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We were missing the trace_hardirqs_on() instrumentation in the nommu
case, resync with the MMU version of the page fault handler to have
this behaving consistently. Also explicitly re-enable IRQs now that
the assembly code isn't doing it for us any more.Signed-off-by: Paul Mundt
