22 Jul, 2005

1 commit


18 Jul, 2005

2 commits


16 Jul, 2005

1 commit


08 Jul, 2005

2 commits


07 Jul, 2005

1 commit

  • This converts the usage of struct of_match to struct of_device_id,
    similar to pci_device_id. This allows a device table to be generated,
    which can be parsed by depmod(8) to generate a map file for module
    loading.

    In order for hotplug to work with macio devices, patches to
    module-init-tools and hotplug must be applied. Those patches are
    available at:

    ftp://ftp.suse.com/pub/people/jeffm/linux/macio-hotplug/

    Signed-off-by: Jeff Mahoney
    Signed-off-by: Linus Torvalds

    Jeff Mahoney
     

06 Jul, 2005

1 commit

  • This patch adds the Freescale MPC86xADS board support. The supported
    devices are SMC UART and 10Mbit ethernet on SCC1.

    The manual for the board says that it "is compatible with the MPC8xxFADS
    for software point of view". That's why this patch extends FADS instead of
    introducing a new platform.

    FEC is not supported as the "combined FCC/FEC ethernet driver" driver by
    Pantelis Antoniou should replace the current FEC driver.

    Signed-off-by: Gennadiy Kurtsman
    Signed-off-by: Andrei Konovalov
    Acked-by: Tom Rini
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Andrei Konovalov
     

04 Jul, 2005

3 commits


01 Jul, 2005

1 commit


30 Jun, 2005

3 commits


29 Jun, 2005

1 commit

  • This patch changes the way serial ports are locked when getting modem
    status. This change is necessary because we will need to atomically
    read the modem status and take action depending on the CTS status.

    Signed-off-by: Russell King

    Russell King
     

28 Jun, 2005

2 commits


27 Jun, 2005

2 commits

  • Add separate files for the different 8250 ISA-based serial boards.

    Looking across all the various architectures, it seems reasonable that
    we can key the availability of the configuration options for these
    beasts to the bus-related symbols (iow, CONFIG_ISA). We also standardise
    the base baud/uart clock rate for these boards - I'm sure that isn't
    architecture specific, but is solely dependent on the crystal fitted
    on the board (which should be the same no matter what type of machine
    its fitted into.)

    Signed-off-by: Russell King

    Russell King
     
  • 68328serial.c does not make use of register_serial/unregister_serial,
    which is traditionally used to register 8250-compatible UARTs with
    the 8250-compatible serial driver.

    Acked-by: David McCullough
    Signed-off-by: Russell King

    Russell King
     

26 Jun, 2005

4 commits


25 Jun, 2005

2 commits


24 Jun, 2005

5 commits


23 Jun, 2005

2 commits


22 Jun, 2005

5 commits

  • Several hardware features of SGI's IOC4 I/O controller chip require
    timing-related driver calculations dependent upon the PCI bus speed. This
    patch enables the core IOC4 driver code to detect the actual bus speed and
    store a value that can later be used by the IOC4 subdrivers as needed.

    Signed-off-by: Brent Casavant
    Acked-by: Pat Gefre
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Brent Casavant
     
  • The SGI IOC4 I/O controller chip drivers are currently all configured by
    CONFIG_BLK_DEV_SGIIOC4. This is undesirable as not all IOC4 hardware features
    are needed by all systems.

    This patch adds two configuration variables, CONFIG_SGI_IOC4 for core IOC4
    driver support (see patch 1/3 in this series for further explanation) and
    CONFIG_SERIAL_SGI_IOC4 to independently enable serial port support.

    Signed-off-by: Brent Casavant
    Acked-by: Pat Gefre
    Acked-by: Jeremy Higdon
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Brent Casavant
     
  • This series of patches reworks the configuration and internal structure
    of the SGI IOC4 I/O controller device drivers.

    These changes are motivated by several factors:

    - The IOC4 chip PCI resources are of mixed use between functions (i.e.
    multiple functions are handled in the same address range, sometimes
    within the same register), muddling resource ownership and initialization
    issues. Centralizing this ownership in a core driver is desirable.

    - The IOC4 chip implements multiple functions (serial, IDE, others not
    yet implemented in the mainline kernel) but is not a multifunction
    PCI device. In order to properly handle device addition and removal
    as well as module insertion and deletion, an intermediary IOC4-specific
    driver layer is needed to handle these operations cleanly.

    - All IOC4 drivers are currently enabled by a single CONFIG value. As
    not all systems need all IOC4 functions, it is desireable to enable
    these drivers independently.

    - The current IOC4 core driver will trigger loading of all function-level
    drivers, as it makes direct calls to them. This situation should be
    reversed (i.e. function-level drivers cause loading of core driver)
    in order to maintain a clear and least-surprise driver loading model.

    - IOC4 hardware design necessitates some driver-level dependency on
    the PCI bus clock speed. Current code assumes a 66MHz bus, but the
    speed should be autodetected and appropriate compensation taken.

    This patch series effects the above changes by a newly and better designed
    IOC4 core driver with which the function-level drivers can register and
    deregister themselves upon module insertion/removal. By tracking these
    modules, device addition/removal is also handled properly. PCI resource
    management and ownership issues are centralized in this core driver, and
    IOC4-wide configuration actions such as bus speed detection are also
    handled in this core driver.

    This patch:

    The SGI IOC4 I/O controller chip implements multiple functions, though it is
    not a multi-function PCI device. Additionally, various PCI resources of the
    IOC4 are shared by multiple hardware functions, and thus resource ownership by
    driver is not clearly delineated. Due to the current driver design, all core
    and subordinate drivers must be loaded, or none, which is undesirable if not
    all IOC4 hardware features are being used.

    This patch reorganizes the IOC4 drivers so that the core driver provides a
    subdriver registration service. Through appropriate callbacks the subdrivers
    can now handle device addition and removal, as well as module insertion and
    deletion (though the IOC4 IDE driver requires further work before module
    deletion will work). The core driver now takes care of allocating PCI
    resources and data which must be shared between subdrivers, to clearly
    delineate module ownership of these items.

    Signed-off-by: Brent Casavant
    Acked-by: Pat Gefre
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Brent Casavant
     
  • This patch allows iSeries to build with CONFIG_PCI=n. This is useful for
    partitions that have only virtual I/O.

    Signed-off-by: Stephen Rothwell
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Stephen Rothwell
     
  • Adds SCC2 pin routing specific to the GP3 board.

    Signed-off-by: Matt Porter
    Signed-off-by: Kumar Gala
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Matt Porter
     

09 Jun, 2005

1 commit


05 Jun, 2005

1 commit

  • - Changed the return value of unknown type to NULL.

    - Deleted the NULL check of dev_id in siu_interrupt().

    - Deleted the NULL check of port->membase in siu_shutdown().

    - Added the NULL check of port->membase to siu_startup().

    - Removed early_uart_ops. Now using vr41xx_siu standerd one.

    - Changed KSEG1ADDR() in siu_console_setup() to ioremap().

    - When uart_add_one_port() failed, changed to set NULL to port->dev.

    Signed-off-by: Yoichi Yuasa
    Cc: Russell King
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Yoichi Yuasa