18 Sep, 2015
1 commit
-
Pull irq updates from Thomas Gleixner:
"This is a rather large update post rc1 due to the final steps of
cleanups and API changes which had to wait for the preparatory patches
to hit your tree.- Regression fixes for ARM GIC irqchips
- Regression fixes and lockdep anotations for renesas irq chips
- The leftovers of the cleanup and preparatory patches which have
been ignored by maintainers- Final conversions of the newly merged users of obsolete APIs
- Final removal of obsolete APIs
- Final removal of ARM artifacts which had been introduced during the
conversion of ARM to the generic interrupt code.- Final split of the irq_data into chip specific and common data to
reflect the needs of hierarchical irq domains.- Treewide removal of the first argument of interrupt flow handlers,
i.e. the irq number, which is not used by the majority of handlers
and simple to retrieve from the other argument the irq descriptor.- A few comment updates and build warning fixes"
* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (40 commits)
arm64: Remove ununsed set_irq_flags
ARM: Remove ununsed set_irq_flags
sh: Kill off set_irq_flags usage
irqchip: Kill off set_irq_flags usage
gpu/drm: Kill off set_irq_flags usage
genirq: Remove irq argument from irq flow handlers
genirq: Move field 'msi_desc' from irq_data into irq_common_data
genirq: Move field 'affinity' from irq_data into irq_common_data
genirq: Move field 'handler_data' from irq_data into irq_common_data
genirq: Move field 'node' from irq_data into irq_common_data
irqchip/gic-v3: Use IRQD_FORWARDED_TO_VCPU flag
irqchip/gic: Use IRQD_FORWARDED_TO_VCPU flag
genirq: Provide IRQD_FORWARDED_TO_VCPU status flag
genirq: Simplify irq_data_to_desc()
genirq: Remove __irq_set_handler_locked()
pinctrl/pistachio: Use irq_set_handler_locked
gpio: vf610: Use irq_set_handler_locked
powerpc/mpc8xx: Use irq_set_handler_locked()
powerpc/ipic: Use irq_set_handler_locked()
powerpc/cpm2: Use irq_set_handler_locked()
...
16 Sep, 2015
3 commits
-
Most interrupt flow handlers do not use the irq argument. Those few
which use it can retrieve the irq number from the irq descriptor.Remove the argument.
Search and replace was done with coccinelle and some extra helper
scripts around it. Thanks to Julia for her help!Signed-off-by: Thomas Gleixner
Cc: Julia Lawall
Cc: Jiang Liu -
Use irq_set_handler_locked() as it avoids a redundant lookup of the
irq descriptor. Search and replacement was done with coccinelle:Signed-off-by: Thomas Gleixner
Cc: Julia Lawall
Cc: Linus Walleij
Cc: linux-gpio@vger.kernel.org -
__irq_set_chip_handler_name_locked() is about to be replaced. Use
irq_set_chip_handler_name_locked() instead.Signed-off-by: Thomas Gleixner
Cc: Linus Walleij
Cc: linux-gpio@vger.kernel.org
14 Sep, 2015
5 commits
-
?SYNTAX ERROR
irq_desc_get_irq_chip() does not exist. It should
be irq_desc_get_chip(). Tested by compiling
s3c2410_defconfig.Cc: Thomas Gleixner
Reported-by: Paul Gortmaker
Signed-off-by: Linus Walleij -
If the gpio driver is confused about the numbers for gpio-ranges,
pinctrl_ready_for_gpio_range() may get called with invalid GPIO
causing a NULL pointer exception. Let's instead provide a warning
that allows fixing the problem and return with error.Signed-off-by: Tony Lindgren
Signed-off-by: Linus Walleij -
There is no reason to break a line shorter than 80 columns.
Signed-off-by: Masahiro Yamada
Signed-off-by: Linus Walleij -
Since commit 323de9efdf3e ("pinctrl: make pinctrl_register() return proper
error code"), pinctrl_register returns an error code rather than NULL on
failure. Update a driver that was introduced more recently.The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)//
@@
expression e,e1,e2;
@@e = pinctrl_register(...)
... when != e = e1
if (
- e == NULL
+ IS_ERR(e)
) {
...
return
- e2
+ PTR_ERR(e)
;
}
//Signed-off-by: Julia Lawall
Acked-by: Baruch Siach
Signed-off-by: Linus Walleij -
Since commit 323de9efdf3e ("pinctrl: make pinctrl_register() return proper
error code"), pinctrl_register returns an error code rather than NULL on
failure. Update some drivers that were introduced more recently.The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)//
@@
expression e,e1,e2;
@@e = pinctrl_register(...)
... when != e = e1
if (
- e == NULL
+ IS_ERR(e)
) {
...
return
- e2
+ PTR_ERR(e)
;
}
//Signed-off-by: Julia Lawall
Signed-off-by: Linus Walleij
05 Sep, 2015
1 commit
-
Pull pin control updates from Linus Walleij:
"This is the bulk of pin control changes for the v4.3 development
cycle.Like with GPIO it's a lot of stuff. If my subsystems are any sign of
the overall tempo of the kernel v4.3 will be a gigantic diff.[ It looks like 4.3 is calmer than 4.2 in most other subsystems, but
we'll see - Linus ]Core changes:
- It is possible configure groups in debugfs.
- Consolidation of chained IRQ handler install/remove replacing all
call sites where irq_set_handler_data() and
irq_set_chained_handler() were done in succession with a combined
call to irq_set_chained_handler_and_data(). This series was
created by Thomas Gleixner after the problem was observed by
Russell King.- Tglx also made another series of patches switching
__irq_set_handler_locked() for irq_set_handler_locked() which is
way cleaner.- Tglx also wrote a good bunch of patches to make use of
irq_desc_get_xxx() accessors and avoid looking up irq_descs from
IRQ numbers. The goal is to get rid of the irq number from the
handlers in the IRQ flow which is nice.Driver feature enhancements:
- Power management support for the SiRF SoC Atlas 7.
- Power down support for the Qualcomm driver.
- Intel Cherryview and Baytrail: switch drivers to use raw spinlocks
in IRQ handlers to play nice with the realtime patch set.- Rework and new modes handling for Qualcomm SPMI-MPP.
- Pinconf power source config for SH PFC.
New drivers and subdrivers:
- A new driver for Conexant Digicolor CX92755.
- A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5,
ProXtream2 and PH1-LD6b SoC pin control support.- Reverse-egineered the S/PDIF settings for the Allwinner sun4i
driver.- Support for Qualcomm Technologies QDF2xxx ARM64 SoCs
- A new Freescale i.mx6ul subdriver.
Cleanup:
- Remove platform data support in a number of SH PFC subdrivers"
* tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits)
pinctrl: at91: fix null pointer dereference
pinctrl: mediatek: Implement wake handler and suspend resume
pinctrl: mediatek: Fix multiple registration issue.
pinctrl: sh-pfc: r8a7794: add USB pin groups
pinctrl: at91: Use generic irq_{request,release}_resources()
pinctrl: cherryview: Use raw_spinlock for locking
pinctrl: baytrail: Use raw_spinlock for locking
pinctrl: imx6ul: Remove .owner field
pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp
pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching
clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks
pinctrl: sun4i: add spdif to pin description.
pinctrl: atlas7: clear ugly branch statements for pull and drivestrength
pinctrl: baytrail: Serialize all register access
pinctrl: baytrail: Drop FSF mailing address
pinctrl: rockchip: only enable gpio clock when it setting
pinctrl/mediatek: fix spelling mistake in dev_err error message
pinctrl: cherryview: Serialize all register access
pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting
pinctrl: nomadik: reflect current input value
...
02 Sep, 2015
1 commit
-
Pull ARM DT updates from Olof Johansson:
"Ladies and gentlemen, we proudly announce to you the latest branch of
ARM device tree contents for the mainline kernel. Come and see, come
and see!No less than twentythree thousand lines of additions! Just imagine the
joy you will have of using your mainline kernel on newly supported
hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or
UniPhier hardware!For those of you feeling less adventurous, added hardware support on
platforms such as TI DM814x and Gumstix Overo platforms might be more
of your liking.We've got something for everyone here!
Ahem. Cough. So, anyway...
This is the usual large batch of DT updates. Lots and lots of smaller
changes, some of the larger ones to point out are:- Rockchip veyron (Chromebook) support, as well as several other new boards
- DRM support on Atmel AT91SAM9N12EK
- USB additions on some Allwinner platforms
- Mediatek MT6580 support
- Freescale i.MX6UL support
- cleanups for Renesas shmobile platforms
- lots of added devices on LPC18xx
- lots of added devices and boards on UniPhierThere's also some dependent code added here, in particular some
branches that are primarily merged through the clock tree"* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits)
ARM: tegra: Add gpio-ranges property
ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114
ARM: tegra: Add Tegra124 PMU support
ARM: tegra: jetson-tk1: Add GK20A GPU DT node
ARM: tegra: venice2: Add GK20A GPU DT node
ARM: tegra: Add IOMMU node to GK20A
ARM: tegra: Add CPU regulator to the Jetson TK1 device tree
ARM: tegra: Add entries for cpufreq on Tegra124
ARM: tegra: Enable the DFLL on the Jetson TK1
ARM: tegra: Add the DFLL to Tegra124 device tree
ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller.
ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes
ARM: dts: rockchip: correct regulator power states for suspend
ARM: dts: rockchip: correct regulator PM properties
ARM: dts: vexpress: Use assigned-clock-parents for sp810
pinctrl: tegra: Only set the gpio range if needed
arm: boot: dts: am4372: add ARM timers and SCU nodes
ARM: dts: AM4372: Add the am4372-rtc compatible string
ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain
ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain
...
31 Aug, 2015
1 commit
-
Not all gpio banks are necessarily enabled, in the current code this can
lead to null pointer dereferences.[ 51.130000] Unable to handle kernel NULL pointer dereference at virtual address 00000058
[ 51.130000] pgd = dee04000
[ 51.130000] [00000058] *pgd=3f66d831, *pte=00000000, *ppte=00000000
[ 51.140000] Internal error: Oops: 17 [#1] ARM
[ 51.140000] Modules linked in:
[ 51.140000] CPU: 0 PID: 1664 Comm: cat Not tainted 4.1.1+ #6
[ 51.140000] Hardware name: Atmel SAMA5
[ 51.140000] task: df6dd880 ti: dec60000 task.ti: dec60000
[ 51.140000] PC is at at91_pinconf_get+0xb4/0x200
[ 51.140000] LR is at at91_pinconf_get+0xb4/0x200
[ 51.140000] pc : [] lr : [] psr: 600f0013
sp : dec61e48 ip : 600f0013 fp : df522538
[ 51.140000] r10: df52250c r9 : 00000058 r8 : 00000068
[ 51.140000] r7 : 00000000 r6 : df53c910 r5 : 00000000 r4 : dec61e7c
[ 51.140000] r3 : 00000000 r2 : c06746d4 r1 : 00000000 r0 : 00000003
[ 51.140000] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
[ 51.140000] Control: 10c53c7d Table: 3ee04059 DAC: 00000015
[ 51.140000] Process cat (pid: 1664, stack limit = 0xdec60208)
[ 51.140000] Stack: (0xdec61e48 to 0xdec62000)
[ 51.140000] 1e40: 00000358 00000000 df522500 ded15f80 c05a9d08 ded15f80
[ 51.140000] 1e60: 0000048c 00000061 df522500 ded15f80 c05a9d08 c01e7304 ded15f80 00000000
[ 51.140000] 1e80: c01e6008 00000060 0000048c c01e6034 c01e5f6c ded15f80 dec61ec0 00000000
[ 51.140000] 1ea0: 00020000 ded6f280 dec61f80 00000001 00000001 c00ae0b8 b6e80000 ded15fb0
[ 51.140000] 1ec0: 00000000 00000000 df4bc974 00000055 00000800 ded6f280 b6e80000 ded6f280
[ 51.140000] 1ee0: ded6f280 00020000 b6e80000 00000000 00020000 c0090dec c0671e1c dec61fb0
[ 51.140000] 1f00: b6f8b510 00000001 00004201 c000924c 00000000 00000003 00000003 00000000
[ 51.140000] 1f20: df4bc940 00022000 00000022 c066e188 b6e7f000 c00836f4 000b6e7f ded6f280
[ 51.140000] 1f40: ded6f280 b6e80000 dec61f80 ded6f280 00020000 c0091508 00000000 00000003
[ 51.140000] 1f60: 00022000 00000000 00000000 ded6f280 ded6f280 00020000 b6e80000 c0091d9c
[ 51.140000] 1f80: 00000000 00000000 ffffffff 00020000 00020000 b6e80000 00000003 c000f124
[ 51.140000] 1fa0: dec60000 c000efa0 00020000 00020000 00000003 b6e80000 00020000 000271c4
[ 51.140000] 1fc0: 00020000 00020000 b6e80000 00000003 7fffe000 00000000 00000000 00020000
[ 51.140000] 1fe0: 00000000 bef50b64 00013835 b6f29c76 400f0030 00000003 00000000 00000000
[ 51.140000] [] (at91_pinconf_get) from [] (at91_pinconf_dbg_show+0x18/0x2c0)
[ 51.140000] [] (at91_pinconf_dbg_show) from [] (pinconf_pins_show+0xc8/0xf8)
[ 51.140000] [] (pinconf_pins_show) from [] (seq_read+0x1a0/0x464)
[ 51.140000] [] (seq_read) from [] (__vfs_read+0x20/0xd0)
[ 51.140000] [] (__vfs_read) from [] (vfs_read+0x7c/0x108)
[ 51.140000] [] (vfs_read) from [] (SyS_read+0x40/0x94)
[ 51.140000] [] (SyS_read) from [] (ret_fast_syscall+0x0/0x3c)
[ 51.140000] Code: eb010ec2 e30a0d08 e34c005a eb0ae5a7 (e5993000)
[ 51.150000] ---[ end trace fb3c370da3ea4794 ]---Fixes: a0b957f306fa ("pinctrl: at91: allow to have disabled gpio bank")
Cc: stable@vger.kernel.org # 3.18
Signed-off-by: David Dueck
Acked-by: Ludovic Desroches
Acked-by: Alexandre Belloni
Acked-by: Nicolas Ferre
Cc: Boris Brezillon
Cc: Jean-Christophe PLAGNIOL-VILLARD
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Linus Walleij
26 Aug, 2015
6 commits
-
This patch implement irq_set_wake to get who is wakeup source and
setup on suspend resume.Signed-off-by: Maoguang Meng
Reviewed-by: Daniel Kurtz
Acked-by: Yingjoe Chen
Acked-by: Hongzhou Yang
Signed-off-by: Linus Walleij -
Since our common driver need support main chip and PMU
at the same time, that means it will register two
pinctrl device, and the pinctrl_desc structure should
be used two times.But pinctrl_desc use global static definition, then
the latest registered pinctrl device will overwrite
the old one's, all members in pinctrl_desc will set to
the new one's, such as name, pins and pins numbers, etc.
This is a bug.Move pinctrl_desc into mtk_pinctrl, assign new value for
each pinctrl device to fix it.Cc: stable@vger.kernel.org # v4.1+
Signed-off-by: Hongzhou Yang
Reviewed-by: Axel Lin
Signed-off-by: Linus Walleij -
Add USB0/1 pin groups to R8A7794 PFC driver.
Signed-off-by: Shinobu Uehara
[Sergei: rebased, renamed, added changelog.]
Signed-off-by: Sergei Shtylyov
Acked-by: Laurent Pinchart
Signed-off-by: Linus Walleij -
The at91-specific irq_{request,release}_resources() callbacks are
identical to the generic ones, modulo the bug fix in 5b76e79c77264899
("gpiolib: irqchip: prevent driver unloading if gpio is used as irq
only").Until commit 8b67a1f0ad1f260f ("gpio: don't override irq_*_resources()
callbacks"), the buggy at91-specific callbacks were never used, though.Hence drop the at91-specific ones in favor of the generic ones.
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Linus Walleij -
When running -rt kernel and an interrupt happens on a GPIO line controlled by
Intel Cherryview/Braswell pinctrl driver we get:BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
Preemption disabled at:[] cpu_startup_entry+0x17f/0x480CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16
...
Call Trace:
[] dump_stack+0x4a/0x61
[] ___might_sleep+0xe7/0x170
[] rt_spin_lock+0x1f/0x50
[] chv_gpio_irq_ack+0x3d/0xa0
[] handle_edge_irq+0x75/0x180
[] generic_handle_irq+0x27/0x40
[] chv_gpio_irq_handler+0x7e/0x110
[] handle_irq+0xaa/0x190
...This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack()
is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock
which in -rt is an rt-mutex causing might_sleep() rightfully to complain about
sleeping function called from invalid context.In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.Suggested-by: Linus Walleij
Signed-off-by: Mika Westerberg
Signed-off-by: Linus Walleij -
The Intel Baytrail pinctrl driver implements irqchip callbacks which are
called with desc->lock raw_spinlock held. In mainline this is fine because
spinlock resolves to raw_spinlock. However, running the same code in -rt we
get:BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
Preemption disabled at:[] cpu_startup_entry+0x17f/0x480CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #13
...
Call Trace:
[] dump_stack+0x4a/0x61
[] ___might_sleep+0xe7/0x170
[] rt_spin_lock+0x1f/0x50
[] byt_gpio_clear_triggering+0x38/0x60
[] byt_irq_mask+0x11/0x20
[] handle_level_irq+0x83/0x150
[] generic_handle_irq+0x27/0x40
[] byt_gpio_irq_handler+0x7f/0xc0
[] handle_irq+0xaa/0x190
...This is because in -rt spinlocks are preemptible so taking the driver
private spinlock in irqchip callbacks causes might_sleep() to trigger.In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.Also shorten the critical section a bit in few places.
Suggested-by: Linus Walleij
Signed-off-by: Mika Westerberg
Signed-off-by: Linus Walleij
25 Aug, 2015
2 commits
-
platform_driver does not need to set an owner as it will be
populated by the driver core.The semantic patch that makes this change is available
in scripts/coccinelle/api/platform_no_drv_owner.cocci.Signed-off-by: Fabio Estevam
Signed-off-by: Linus Walleij -
Group names should be smc0_nand_grp and smc0_nor_grp, otherwise you'll
get errors like this if you try to pinmux them via the devicetree:
zynq-pinctrl 700.pinctrl: invalid group "smc0_nand_grp" for function "smc0_nand"Probably a typo while creating these tables.
Signed-off-by: Mike Looijmans
Acked-by: Sören Brinkmann
Acked-by: Moritz Fischer
Signed-off-by: Linus Walleij
24 Aug, 2015
1 commit
-
The pfc in the R8A7790 (and probably others in the R-Car gen 2 family)
supports switching SDHI signals between 3.3V and 1.8V nominal voltage,
and the SD driver should do that when switching to and from UHS modes.Add a flag for pins that have configurable I/O voltage and SoC
operations to get and set the nominal voltage. Implement the pinconf
power-source parameter using these operations.Signed-off-by: Ben Hutchings
Acked-by: Laurent Pinchart
Signed-off-by: Linus Walleij
13 Aug, 2015
9 commits
-
If the gpio DT node has the gpio-ranges property, the range will be
added by the gpio core and doesn't need to be added by the pinctrl
driver.By having the gpio-ranges property, we have an explicit dependency from
the gpio node to the pinctrl node and we can stop using the deprecated
pinctrl_add_gpio_range() function.Signed-off-by: Tomeu Vizoso
Acked-by: Stephen Warren
Acked-by: Linus Walleij
Signed-off-by: Thierry Reding -
Signed-off-by: Marcus Cooper
Reviewed-by: Hans de Goede
Signed-off-by: Linus Walleij -
To set/get atlas7 pull & drive strength, we use lots of if/else
to check pad type. But except mask value or immediate value, all
actions in these conditional branches are the same.
So we use predefined pull info table and drive strength table
to reduce these redundancy code.Signed-off-by: Wei Chen
Signed-off-by: Barry Song
Signed-off-by: Linus Walleij -
There is a hardware issue in Intel Baytrail where concurrent GPIO register
access might result reads of 0xffffffff and writes might get dropped
completely.Prevent this from happening by taking the serializing lock in all places
where it is possible that more than one thread might be accessing the
hardware concurrently.Signed-off-by: Mika Westerberg
Signed-off-by: Linus Walleij -
The FSF address is already mentioned in the COPYING file. No need to
duplicate that information to individual files.Signed-off-by: Mika Westerberg
Signed-off-by: Linus Walleij -
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it settingSigned-off-by: Lin Huang
Reviewed-by: Heiko Stuebner
Reviewed-by: Douglas Anderson
Tested-by: Douglas Anderson
Signed-off-by: Linus Walleij -
Trivial change, fix spelling mistake 'invaild' -> 'invalid' in
dev_err message.Signed-off-by: Colin Ian King
Acked-by: Hongzhou Yang
Signed-off-by: Linus Walleij -
There is a hardware issue in Intel Braswell/Cherryview where concurrent
GPIO register access might results reads of 0xffffffff and writes might get
dropped.Prevent this from happening by taking the serializing lock for all places
where it is possible that more than one thread might be accessing the
hardware concurrently.Signed-off-by: Mika Westerberg
Signed-off-by: Linus Walleij -
The initial version of this driver missed to add I2C ch6 pin-muxing.
Signed-off-by: Masahiro Yamada
Signed-off-by: Linus Walleij
11 Aug, 2015
1 commit
-
Let us see the current value on the input line in debugfs.
Signed-off-by: Linus Walleij
03 Aug, 2015
1 commit
-
These are user-visible strings, so can exceed 80 columns.
Signed-off-by: Masahiro Yamada
Signed-off-by: Linus Walleij
28 Jul, 2015
3 commits
-
We had not implemented the pm interface of atlas7 pinctrl
and gpio drivers. So when system resumes from sleep, all
pin configuration and gpio status will be lost.Now, we implement these interfaces to support pm.
At the same time, this patch also drops a lot of if-else
by look-up table for getting and setting pull.Signed-off-by: Wei Chen
Signed-off-by: Barry Song
Signed-off-by: Linus Walleij -
Split the UART pin groups so we can activate RX/TX, CTS/RTS and
the modem pins (DCD, DSR, RI, DTR) as three different groups
with function u0.Signed-off-by: Linus Walleij
-
set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOENFor IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.Signed-off-by: Rob Herring
Cc: Stephen Warren
Cc: Lee Jones
Cc: Matthias Brugger
Cc: Tomasz Figa
Cc: Thomas Abraham
Cc: Kukjin Kim
Cc: Krzysztof Kozlowski
Cc: linux-gpio@vger.kernel.org
Cc: linux-rpi-kernel@lists.infradead.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Signed-off-by: Linus Walleij
27 Jul, 2015
5 commits
-
We no longer have to do GPIO initialization before the
pinctrl initialization, instead we can initialize the pinctrl
portions of the driver first and then the GPIO. Thus we can
move GPIO initialization to a subsystem_initcall(), but
not yet to a device_initcall().Signed-off-by: Linus Walleij
-
This gets the GPIO ranges out of the driver and into the device
tree where they belong. Standard DT bindings already exist for
this. Since no systems with this are deployed we can just augment
all device trees and the drivers at the same time and simplify
the world.This also defines the array of GPIO chips related to the pin
controller.Cc: arm@kernel.org
Acked-by: Olof Johansson
Signed-off-by: Linus Walleij -
The current interrupt parsing code was working by accident, because the
default was actually parsing the first node of interrupts.While that was mostly working (and the flags were actually ignored), this
binding has never been documented, and doesn't work with SoCs that have
multiple interrupt banks anyway.Add a proper interrupt xlate function, that uses the same description than
the GPIOs ( ), that will make things less confusing.The EINT number will still be used as the hwirq number, but won't be
exposed through the DT.Signed-off-by: Maxime Ripard
Reviewed-by: Hans de Goede
Signed-off-by: Linus Walleij -
Use dev_err() rather than pr_err() to display the error message.
pinctrl_dev_get_name(pctldev) is no longer necessary because
dev_err() shows which device the message is related to.Signed-off-by: Masahiro Yamada
Signed-off-by: Linus Walleij -
Use dev_err() rather than pr_err() to display the error message.
(Besides, dev_err() is already used 7 lines below in this function.)Also, drop the redundant information "on %s" because dev_err() shows
which device the message is related to.Signed-off-by: Masahiro Yamada
Signed-off-by: Linus Walleij
