Eric Lee / smarc-fsl-linux-kernel

08 Jan, 2020

1 commit

  • 6f69e2a33   phy: lantiq: vrx200-pcie: Remove unneeded semicolon ... Browse Code »

    Fixes coccicheck warning:

    drivers/phy/lantiq/phy-lantiq-vrx200-pcie.c:389:2-3: Unneeded semicolon

    Fixes: e52a632195bf ("phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY")

    Reported-by: Hulk Robot
    Signed-off-by: Ma Feng
    Signed-off-by: Kishon Vijay Abraham I

    Ma Feng
     

31 Oct, 2019

1 commit

23 Aug, 2019

1 commit

  • e52a63219   phy: lantiq: vrx200-pcie: add a driver for the Lantiq VRX200 PCIe PHY ... Browse Code »

    The Lantiq VRX200 SoCs embed a PCIe PHY in the "sram" bus. Unlike most
    other IP blocks on this SoC the register values are only 16-bit wide.
    Like other IP blocks on this SoC the register values are in big endian.

    The PHY embeds a PLL which can be configured in various modes. Only the
    36MHz mode is supported for now, the other modes can be implemented when
    there's a board which actually needs them. OpenWrt uses the out-of-tree
    vendor driver and all supported boards there only need the 36MHz mode.

    There are two input clocks:
    - the "pdi" clock enables the register access
    - the "phy" clock is the clock input and enables the internal PLL

    There are two reset lines:
    - "phy" resets the PHY itself
    - the "pcie" reset line is shared between the PHY and the PCIe
    controller

    While the VRX200 SoC has only one PCIe controller and PHY the ARX300
    uses two identical PCIe controllers and PHYs which are compatible with
    the PCIe controller and PHY on VRX200.
    Add a driver for this PHY so PCIe support can be enabled on these SoCs.

    Signed-off-by: Martin Blumenstingl
    Signed-off-by: Kishon Vijay Abraham I

    Martin Blumenstingl