Eric Lee / smarc-fsl-linux-kernel

29 Jul, 2020

1 commit

  • 5345ede4a   drivers/perf: Prevent forced unbinding of PMU drivers ... Browse Code »

    [ Upstream commit f32ed8eb0e3f0d0ef4ddb854554d60ca5863a9f9 ]

    Forcefully unbinding PMU drivers during perf sampling will lead to
    a kernel panic, because the perf upper-layer framework call a NULL
    pointer in this situation.

    To solve this issue, "suppress_bind_attrs" should be set to true, so
    that bind/unbind can be disabled via sysfs and prevent unbinding PMU
    drivers during perf sampling.

    Signed-off-by: Qi Liu
    Reviewed-by: John Garry
    Link: https://lore.kernel.org/r/1594975763-32966-1-git-send-email-liuqi115@huawei.com
    Signed-off-by: Will Deacon
    Signed-off-by: Sasha Levin

    Qi Liu
     

21 Jan, 2019

1 commit

  • 306563985   For drivers that do not support context exclusion let's advertise the ... Browse Code »

    PERF_PMU_CAP_NO_EXCLUDE capability. This ensures that perf will
    prevent us from handling events where any exclusion flags are set.
    Let's also remove the now unnecessary check for exclusion flags.

    Signed-off-by: Andrew Murray
    Signed-off-by: Peter Zijlstra (Intel)
    Acked-by: Will Deacon
    Cc: Arnaldo Carvalho de Melo
    Cc: Benjamin Herrenschmidt
    Cc: Borislav Petkov
    Cc: Ivan Kokshaysky
    Cc: Linus Torvalds
    Cc: Mark Rutland
    Cc: Matt Turner
    Cc: Michael Ellerman
    Cc: Paul Mackerras
    Cc: Peter Zijlstra
    Cc: Richard Henderson
    Cc: Russell King
    Cc: Sascha Hauer
    Cc: Shawn Guo
    Cc: Thomas Gleixner
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linuxppc-dev@lists.ozlabs.org
    Cc: robin.murphy@arm.com
    Cc: suzuki.poulose@arm.com
    Link: https://lkml.kernel.org/r/1547128414-50693-8-git-send-email-andrew.murray@arm.com
    Signed-off-by: Ingo Molnar

    Andrew Murray
     

06 Dec, 2018

1 commit

  • 69c32972d   drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver ... Browse Code »

    This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
    Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4
    counters. All counters lack overflow interrupt and are
    sampled periodically.

    Reviewed-by: Suzuki K Poulose
    Signed-off-by: Ganapatrao Kulkarni
    [will: consistent enum cpuhp_state naming]
    Signed-off-by: Will Deacon

    Kulkarni, Ganapatrao