Eric Lee / smarc-fsl-linux-kernel

12 Feb, 2019

1 commit

  • a17fd125c   reset: Add driver for gpio-controlled reset pins ... Browse Code »

    This driver implements a reset controller device that toggle a gpio
    connected to a reset pin of a peripheral IC. The delay between assertion
    and de-assertion of the reset signal can be configured via device tree.

    Signed-off-by: Philipp Zabel
    Reviewed-by: Stephen Warren
    Reviewed-by: Pavel Machek
    Signed-off-by: Shawn Guo

    Philipp Zabel
     

02 Nov, 2017

1 commit

  • b24413180   License cleanup: add SPDX GPL-2.0 license identifier to files with no license ... Browse Code »

    Many source files in the tree are missing licensing information, which
    makes it harder for compliance tools to determine the correct license.

    By default all files without license information are under the default
    license of the kernel, which is GPL version 2.

    Update the files which contain no license information with the 'GPL-2.0'
    SPDX license identifier. The SPDX identifier is a legally binding
    shorthand, which can be used instead of the full boiler plate text.

    This patch is based on work done by Thomas Gleixner and Kate Stewart and
    Philippe Ombredanne.

    How this work was done:

    Patches were generated and checked against linux-4.14-rc6 for a subset of
    the use cases:
    - file had no licensing information it it.
    - file was a */uapi/* one with no licensing information in it,
    - file was a */uapi/* one with existing licensing information,

    Further patches will be generated in subsequent months to fix up cases
    where non-standard license headers were used, and references to license
    had to be inferred by heuristics based on keywords.

    The analysis to determine which SPDX License Identifier to be applied to
    a file was done in a spreadsheet of side by side results from of the
    output of two independent scanners (ScanCode & Windriver) producing SPDX
    tag:value files created by Philippe Ombredanne. Philippe prepared the
    base worksheet, and did an initial spot review of a few 1000 files.

    The 4.13 kernel was the starting point of the analysis with 60,537 files
    assessed. Kate Stewart did a file by file comparison of the scanner
    results in the spreadsheet to determine which SPDX license identifier(s)
    to be applied to the file. She confirmed any determination that was not
    immediately clear with lawyers working with the Linux Foundation.

    Criteria used to select files for SPDX license identifier tagging was:
    - Files considered eligible had to be source code files.
    - Make and config files were included as candidates if they contained >5
    lines of source
    - File already had some variant of a license header in it (even if
    Reviewed-by: Philippe Ombredanne
    Reviewed-by: Thomas Gleixner
    Signed-off-by: Greg Kroah-Hartman

    Greg Kroah-Hartman
     

18 Sep, 2017

1 commit

16 Sep, 2017

1 commit

  • 731841307   Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus ... Browse Code »

    Pull MIPS updates from Ralf Baechle:
    "This is the main pull request for 4.14 for MIPS; below a summary of
    the non-merge commits:

    CM:
    - Rename mips_cm_base to mips_gcr_base
    - Specify register size when generating accessors
    - Use BIT/GENMASK for register fields, order & drop shifts
    - Add cluster & block args to mips_cm_lock_other()

    CPC:
    - Use common CPS accessor generation macros
    - Use BIT/GENMASK for register fields, order & drop shifts
    - Introduce register modify (set/clear/change) accessors
    - Use change_*, set_* & clear_* where appropriate
    - Add CM/CPC 3.5 register definitions
    - Use GlobalNumber macros rather than magic numbers
    - Have asm/mips-cps.h include CM & CPC headers
    - Cluster support for topology functions
    - Detect CPUs in secondary clusters

    CPS:
    - Read GIC_VL_IDENT directly, not via irqchip driver

    DMA:
    - Consolidate coherent and non-coherent dma_alloc code
    - Don't use dma_cache_sync to implement fd_cacheflush

    FPU emulation / FP assist code:
    - Another series of 14 commits fixing corner cases such as NaN
    propgagation and other special input values.
    - Zero bits 32-63 of the result for a CLASS.D instruction.
    - Enhanced statics via debugfs
    - Do not use bools for arithmetic. GCC 7.1 moans about this.
    - Correct user fault_addr type

    Generic MIPS:
    - Enhancement of stack backtraces
    - Cleanup from non-existing options
    - Handle non word sized instructions when examining frame
    - Fix detection and decoding of ADDIUSP instruction
    - Fix decoding of SWSP16 instruction
    - Refactor handling of stack pointer in get_frame_info
    - Remove unreachable code from force_fcr31_sig()
    - Convert to using %pOF instead of full_name
    - Remove the R6000 support.
    - Move FP code from *_switch.S to *_fpu.S
    - Remove unused ST_OFF from r2300_switch.S
    - Allow platform to specify multiple its.S files
    - Add #includes to various files to ensure code builds reliable and
    without warning..
    - Remove __invalidate_kernel_vmap_range
    - Remove plat_timer_setup
    - Declare various variables & functions static
    - Abstract CPU core & VP(E) ID access through accessor functions
    - Store core & VP IDs in GlobalNumber-style variable
    - Unify checks for sibling CPUs
    - Add CPU cluster number accessors
    - Prevent direct use of generic_defconfig
    - Make CONFIG_MIPS_MT_SMP default y
    - Add __ioread64_copy
    - Remove unnecessary inclusions of linux/irqchip/mips-gic.h

    GIC:
    - Introduce asm/mips-gic.h with accessor functions
    - Use new GIC accessor functions in mips-gic-timer
    - Remove counter access functions from irq-mips-gic.c
    - Remove gic_read_local_vp_id() from irq-mips-gic.c
    - Simplify shared interrupt pending/mask reads in irq-mips-gic.c
    - Simplify gic_local_irq_domain_map() in irq-mips-gic.c
    - Drop gic_(re)set_mask() functions in irq-mips-gic.c
    - Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
    gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
    - Convert remaining shared reg access, local int mask access and
    remaining local reg access to new accessors
    - Move GIC_LOCAL_INT_* to asm/mips-gic.h
    - Remove GIC_CPU_INT* macros from irq-mips-gic.c
    - Move various definitions to the driver
    - Remove gic_get_usm_range()
    - Remove __gic_irq_dispatch() forward declaration
    - Remove gic_init()
    - Use mips_gic_present() in place of gic_present and remove
    gic_present
    - Move gic_get_c0_*_int() to asm/mips-gic.h
    - Remove linux/irqchip/mips-gic.h
    - Inline __gic_init()
    - Inline gic_basic_init()
    - Make pcpu_masks a per-cpu variable
    - Use pcpu_masks to avoid reading GIC_SH_MASK*
    - Clean up mti, reserved-cpu-vectors handling
    - Use cpumask_first_and() in gic_set_affinity()
    - Let the core set struct irq_common_data affinity

    microMIPS:
    - Fix microMIPS stack unwinding on big endian systems

    MIPS-GIC:
    - SYNC after enabling GIC region

    NUMA:
    - Remove the unused parent_node() macro

    R6:
    - Constify r2_decoder_tables
    - Add accessor & bit definitions for GlobalNumber

    SMP:
    - Constify smp ops
    - Allow boot_secondary SMP op to return errors

    VDSO:
    - Drop gic_get_usm_range() usage
    - Avoid use of linux/irqchip/mips-gic.h

    Platform changes:

    Alchemy:
    - Add devboard machine type to cpuinfo
    - update cpu feature overrides
    - Threaded carddetect irqs for devboards

    AR7:
    - allow NULL clock for clk_get_rate

    BCM63xx:
    - Fix ENETDMA_6345_MAXBURST_REG offset
    - Allow NULL clock for clk_get_rate

    CI20:
    - Enable GPIO and RTC drivers in defconfig
    - Add ethernet and fixed-regulator nodes to DTS

    Generic platform:
    - Move Boston and NI 169445 FIT image source to their own files
    - Include asm/bootinfo.h for plat_fdt_relocated()
    - Include asm/time.h for get_c0_*_int()
    - Include asm/bootinfo.h for plat_fdt_relocated()
    - Include asm/time.h for get_c0_*_int()
    - Allow filtering enabled boards by requirements
    - Don't explicitly disable CONFIG_USB_SUPPORT
    - Bump default NR_CPUS to 16

    JZ4700:
    - Probe the jz4740-rtc driver from devicetree

    Lantiq:
    - Drop check of boot select from the spi-falcon driver.
    - Drop check of boot select from the lantiq-flash MTD driver.
    - Access boot cause register in the watchdog driver through regmap
    - Add device tree binding documentation for the watchdog driver
    - Add docs for the RCU DT bindings.
    - Convert the fpi bus driver to a platform_driver
    - Remove ltq_reset_cause() and ltq_boot_select(
    - Switch to a proper reset driver
    - Switch to a new drivers/soc GPHY driver
    - Add an USB PHY driver for the Lantiq SoCs using the RCU module
    - Use of_platform_default_populate instead of __dt_register_buses
    - Enable MFD_SYSCON to be able to use it for the RCU MFD
    - Replace ltq_boot_select() with dummy implementation.

    Loongson 2F:
    - Allow NULL clock for clk_get_rate

    Malta:
    - Use new GIC accessor functions

    NI 169445:
    - Add support for NI 169445 board.
    - Only include in 32r2el kernels

    Octeon:
    - Add support for watchdog of 78XX SOCs.
    - Add support for watchdog of CN68XX SOCs.
    - Expose support for mips32r1, mips32r2 and mips64r1
    - Enable more drivers in config file
    - Add support for accessing the boot vector.
    - Remove old boot vector code from watchdog driver
    - Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
    - Make CSR functions node aware.
    - Allow access to CIU3 IRQ domains.
    - Misc cleanups in the watchdog driver

    Omega2+:
    - New board, add support and defconfig

    Pistachio:
    - Enable Root FS on NFS in defconfig

    Ralink:
    - Add Mediatek MT7628A SoC
    - Allow NULL clock for clk_get_rate
    - Explicitly request exclusive reset control in the pci-mt7620 PCI driver.

    SEAD3:
    - Only include in 32 bit kernels by default

    VoCore:
    - Add VoCore as a vendor t0 dt-bindings
    - Add defconfig file"

    * '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
    MIPS: Refactor handling of stack pointer in get_frame_info
    MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
    MIPS: microMIPS: Fix decoding of swsp16 instruction
    MIPS: microMIPS: Fix decoding of addiusp instruction
    MIPS: microMIPS: Fix detection of addiusp instruction
    MIPS: Handle non word sized instructions when examining frame
    MIPS: ralink: allow NULL clock for clk_get_rate
    MIPS: Loongson 2F: allow NULL clock for clk_get_rate
    MIPS: BCM63XX: allow NULL clock for clk_get_rate
    MIPS: AR7: allow NULL clock for clk_get_rate
    MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
    mips: Save all registers when saving the frame
    MIPS: Add DWARF unwinding to assembly
    MIPS: Make SAVE_SOME more standard
    MIPS: Fix issues in backtraces
    MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
    MIPS: Ci20: Enable RTC driver
    watchdog: octeon-wdt: Add support for 78XX SOCs.
    watchdog: octeon-wdt: Add support for cn68XX SOCs.
    watchdog: octeon-wdt: File cleaning.
    ...

    Linus Torvalds
     

05 Sep, 2017

1 commit

  • 79797b6fa   reset: Add a reset controller driver for the Lantiq XWAY based SoCs ... Browse Code »

    The reset controllers (on xRX200 and newer SoCs have two of them) are
    provided by the RCU module. This was initially implemented as a simple
    reset controller. However, the RCU module provides more functionality
    (ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
    The old reset controller driver implementation from
    arch/mips/lantiq/xway/reset.c did not honor this fact.

    For some devices the request and the status bits are different.

    Signed-off-by: Martin Blumenstingl
    Signed-off-by: Hauke Mehrtens
    Reviewed-by: Andy Shevchenko
    Acked-by: Philipp Zabel
    Acked-by: Rob Herring
    Cc: john@phrozen.org
    Cc: kishon@ti.com
    Cc: mark.rutland@arm.com
    Cc: linux-mips@linux-mips.org
    Cc: linux-mtd@lists.infradead.org
    Cc: linux-watchdog@vger.kernel.org
    Cc: devicetree@vger.kernel.org
    Cc: linux-spi@vger.kernel.org
    Patchwork: https://patchwork.linux-mips.org/patch/17125/
    Signed-off-by: Ralf Baechle

    Martin Blumenstingl
     

07 Aug, 2017

1 commit

20 Jul, 2017

1 commit

06 Jun, 2017

1 commit

  • 28df169b9   reset: Add the TI SCI reset driver ... Browse Code »

    Some TI Keystone family of SoCs contain a system controller (like the
    Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage
    the low-level device control (like clocks, resets etc) for the various
    hardware modules present on the SoC. These device control operations
    are provided to the host processor OS through a communication protocol
    called the TI System Control Interface (TI SCI) protocol.

    This patch adds a reset driver that communicates to the system
    controller over the TI SCI protocol for performing reset management
    of various devices present on the SoC. Various reset functionalities
    are achieved by the means of different TI SCI device operations
    provided by the TI SCI framework.

    Signed-off-by: Andrew F. Davis
    [s-anna@ti.com: documentation changes, revised commit message]
    Signed-off-by: Suman Anna
    Signed-off-by: Nishanth Menon
    Acked-by: Santosh Shilimkar
    [p.zabel@pengutronix.de: const struct reset_control_ops]
    Signed-off-by: Philipp Zabel

    Andrew F. Davis
     

24 May, 2017

2 commits

15 Mar, 2017

2 commits

  • 627006820   reset: Add Altera Arria10 SR Reset Controller ... Browse Code »

    This patch adds the reset controller functionality for
    Peripheral PHYs to the Arria10 System Resource Chip.

    Signed-off-by: Thor Thayer
    Signed-off-by: Philipp Zabel

    Thor Thayer
     
  • abf97755a   reset: Add i.MX7 SRC reset driver ... Browse Code »

    Add reset controller driver exposing various reset faculties,
    implemented by System Reset Controller IP block.

    Cc: Lucas Stach
    Cc: Mark Rutland
    Cc: devicetree@vger.kernel.org
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-arm-kernel@lists.infradead.org
    Signed-off-by: Andrey Smirnov
    Acked-by: Rob Herring
    Signed-off-by: Philipp Zabel

    Andrey Smirnov
     

20 Jan, 2017

1 commit

18 Nov, 2016

1 commit

30 Aug, 2016

6 commits

25 Aug, 2016

4 commits

24 Aug, 2016

2 commits

30 Jun, 2016

1 commit

  • cc7c2bb14   reset: add TI SYSCON based reset driver ... Browse Code »

    Add a reset-controller driver for performing reset management of
    various devices present on the SoC, with the reset registers shared
    between devices in a common register memory space. This driver uses
    the syscon/regmap frameworks to actually implement the various reset
    functionalities needed by the reset consumer devices.

    Signed-off-by: Andrew F. Davis
    [s-anna@ti.com: add documentation, syscon name change]
    Signed-off-by: Suman Anna
    Signed-off-by: Philipp Zabel

    Andrew F. Davis
     

01 Jun, 2016

1 commit

01 Apr, 2016

1 commit

05 Feb, 2016

1 commit

20 Nov, 2015

1 commit

16 Nov, 2015

1 commit

16 Aug, 2015

1 commit

04 Aug, 2015

2 commits

03 Aug, 2015

1 commit

  • c392b65ba   reset: add driver for lpc18xx rgu ... Browse Code »

    Add reset driver for the Reset Generation Unit (RGU) found on NXP
    LPC18xx and LPC43xx devies. This reset controller features up to 64
    reset lines connected to different blocks and peripheral in the SoC.
    Most reset lines on the controller are self clearing except for
    those dealing with the Cortex-M0 cores on LPC43xx devices.

    This driver also registers a restart handler that can be used to
    reset the entire device.

    Signed-off-by: Joachim Eastwood
    Signed-off-by: Philipp Zabel

    Joachim Eastwood
     

20 Oct, 2014

1 commit

26 Apr, 2014

1 commit

  • a39a49393   reset: add driver for socfpga ... Browse Code »

    Add a reset-controller driver for the socfpga platform.
    The reset-controller has four banks with up to 32 entries all encapsulated in
    one module block.

    Signed-off-by: Steffen Trumtrar
    Acked-by: Philipp Zabel
    Signed-off-by: Dinh Nguyen
    ---

    Notes:
    Changes since v2:
    - remove superfluous ret in probe function
    - add Acked-by

    Changes since v1:
    - use BITS_PER_LONG everywhere instead of MAX_BANK_WIDTH
    - print pdev->dev.of_node->full_name on error
    - use proper IS_ERR/PTR_ERR

    Steffen Trumtrar
     

11 Mar, 2014

1 commit

  • e5d76075d   drivers: reset: STi SoC system configuration reset controller support ... Browse Code »

    This patch adds a reset controller implementation for STMicroelectronics
    STi family SoCs; it allows a group of related reset like controls found
    in multiple system configuration registers to be represented by a single
    controller device. System configuration registers are accessed through
    the regmap framework and the mfd/syscon driver.

    The implementation optionally supports waiting for the reset action to
    be acknowledged in a separate status register and supports both
    active high and active low reset lines. These properties are common across
    all the reset channels in a specific reset controller instance, hence
    all channels in a paritcular controller are expected to behave in the
    same way.

    Signed-off-by: Stephen Gallimore
    Signed-off-by: Srinivas Kandagatla
    Acked-by: Philipp Zabel

    Stephen Gallimore
     

23 Nov, 2013

1 commit

  • 8f1ae77f4   reset: Add Allwinner SoCs Reset Controller Driver ... Browse Code »

    The Allwinner A31 and most of the other Allwinner SoCs have an IP
    maintaining a few other IPs in the SoC in reset by default. Among these
    IPs are the A31's High Speed Timers, hence why we can't use the regular
    driver construct in every cases, and need to call the registering
    function directly during machine initialisation.

    Apart from this, the implementation is fairly straightforward, and could
    easily be moved to a generic MMIO-based reset controller driver if the
    need ever arise.

    Signed-off-by: Maxime Ripard
    Acked-by: Philipp Zabel

    Maxime Ripard