02 May, 2019
3 commits
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Add delay cell support for fspi to set calibrated value to DLL register
for different clock frequency.Signed-off-by: Han Xu
(cherry picked from commit 5b608b98697668bd11563febba89bd0eea1c1b26)
Signed-off-by: Arulpandiyan Vadivel
Signed-off-by: Shrikant Bobade
(cherry picked from commit 75bd56659a626a2f013e7ec3e9019eede68bd315) -
Use ioremap_wc to handle unaligned qspi AHB read. Remove the previous
SW alignment handle for neat code.Signed-off-by: Han Xu
Signed-off-by: Arulpandiyan Vadivel
Signed-off-by: Shrikant Bobade
(cherry picked from commit 07c7e72b0ed05beaf2c07d8e098e18c1e48ec634) -
Use ioremap_wc to handle unaligned flexspi AHB read. Remove the previous
SW alignment handle for neat code.Signed-off-by: Han Xu
Signed-off-by: Arulpandiyan Vadivel
Signed-off-by: Shrikant Bobade
(cherry picked from commit c180c525fd7b834ea0e07be4ca79fb8986a214cf)
25 Apr, 2019
1 commit
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prep/unprep functions were not added in new spi_nor_resume function.
Signed-off-by: Han Xu
20 Apr, 2019
4 commits
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use the run-time pm rather than en/disable clock in chip select function.
Signed-off-by: Han Xu
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enable the macros for mx8 platforms
Signed-off-by: Han Xu
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- Implemented the SFDP lut to get the correct chip information
- Changed the default read mode from normal read to Quad DDR
- Enabled the AHB prefetch after chip probed
- Limited the highest clock rate for iMX8MMSigned-off-by: Han Xu
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Enable FlexSPI driver on i.MX8MM EVK.
Signed-off-by: Han Xu
18 Apr, 2019
32 commits
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enable the quad_only quirk for the platforms only support up to Quad
I/O.Signed-off-by: Han Xu
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iMX8MM DDR3L validation board uses GD25LQ16 as spi-nor chip, but its
id is incorrect in ids table, so add a new id and parameters with the
same name into the ids table. For the same name of the chip info, the
log following we can ignore.LOG: m25p80 spi0.0: found gd25q16, expected gd25q16
Signed-off-by: Clark Wang
Reviewed-by: Fugang Duan
Signed-off-by: Arulpandiyan Vadivel -
Flexspi registers cannot be reset to default value, reset all FLASHxCR2
registers to 0 to avoid read data with invalid LUT commands.Signed-off-by: Han Xu
Signed-off-by: Arulpandiyan Vadivel -
The dummy pad settings should be align with data access mode, such as
set to PAD4 for all Quad read.Signed-off-by: Han Xu
Signed-off-by: Arulpandiyan Vadivel -
i.MX6QP and i.MX6ULL clock defination was missed in devdata.
Signed-off-by: Han Xu
(cherry picked from commit 1e6f6478d9f47f3c786afb9648f6947c53188c97)
Signed-off-by: Vipul Kumar -
release the HIGH_FREQ request was done in runtime suspend, disable
autosuspend and disable the runtime in NAND probe error path.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
acquire/release dma in runtime pm resume/suspend to proper get/put dma
resources.BuildInfo:
- SCFW 60e110f9, IMX-MKIMAGE e131af10, ATF
- U-Boot 2017.03-imx_4.9.51_8qm_beta1_8qxp_alpha+gfcc9bdcSigned-off-by: Han Xu
Signed-off-by: Vipul Kumar -
mtd->priv is no longer pointing to the struct nand_chip it is attached
to. Replace those accesses by mtd_to_nand() calls.Signed-off-by: Octavian Purdila
Signed-off-by: Vipul Kumar -
support NAND on imx6ull
Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
missed the brackets for bch legacy support, which leads the large oob
nand bch setting to wrong path.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
Provide an option in DT to use legacy bch geometry, which compatible
with the 3.10 kernel bch setting. To enable the feature, adding
"fsl,legacy-bch-geometry" under gpmi-nand node.NOTICE: The feature must be enabled/disabled in both u-boot and kernel.
Conflicts:
drivers/mtd/nand/gpmi-nand/gpmi-nand.hSigned-off-by: Han Xu
(cherry picked from commit 4d28b1693905526558892d40525763e6bc4469e4)
Signed-off-by: Vipul Kumar -
fix the potential integer overflow issue found by coverify.
Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
For backward compatibility, kobs-ng need to know if the driver use
legacy raw mode or new bch layout raw mode, add a new flag in debugfs to
indicate the raw access mode.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
support the bch layout with dedicate ecc for meta
Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
If the master mtd does not have any slave mtd partitions,
and its numeraseregions is one(only has one erease block), and
we attach the master mtd with : ubiattach -m 0 -d 0We will meet the error:
-------------------------------------------------------
root@freescale ~$ ubiattach /dev/ubi_ctrl -m 0 -d 0
UBI: attaching mtd0 to ubi0
UBI error: io_init: multiple regions, not implemented
ubiattach: error!: cannot attach mtd0
error 22 (Invalid argument)
-------------------------------------------------------In fact, if there is only one "erase block", we should not
prevent the attach.This patch fixes it.
Signed-off-by: Huang Shijie
(cherry picked from commit 361cdc47fc4c4db31c5485560cdabd94f409bd81)
(cherry picked from commit ebee7d74914fad3cf7223af84496811c9d2488a1)Signed-off-by: Vipul Kumar
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i.MX6SX Sabreauto board enabled both NAND and QSPI1 drivrers, and by
default, NAND driver built first in kernel compiling, and it would be load
first when Kernel brought up.Since we could not guarantee all boards mounted NAND chips, we wish the
Kernel could load QSPI driver first, when system mapped QSPI and NAND, the
mtd device index won't change dynamically, otherwise, the mfgtool may write
images to the inappropriate storage devices.The code change moved the SPI driver at the prior position of NAND driver
in Makefile to solve this issue.Signed-off-by: Allen Xu
(cherry picked from commit 3d2d5724f7a2968b40c2ea0a70c09a3214da1496)
(cherry picked from commit b03ee70fdd1dfaa3be61817eb49d01d49cb107d3)
(Vipul: Fixed merge conflicts)
Signed-off-by: Vipul Kumar -
fix the bch setting issue when system suspend/resume, the bch geometry
only need to be saved to debugfs in driver initial stageSigned-off-by: Han Xu
(cherry picked from commit 3b4f7178854e428fb5ef08d554b13abe4f27c533)
Signed-off-by: Vipul Kumar -
The erase threshold should be set to ecc_strength for these platforms.
Signed-off-by: Han Xu
(cherry picked from commit f46d113a02f5375c38fc9aba88c587fd672a30c4)
Signed-off-by: Vipul Kumar -
The cod change updated the NAND driver BCH ECC layout algorithm to
support large oob size NAND chips(oob > 1024 bytes) and proposed a new
way to set ECC layout.Current implementation requires each chunk size larger than oob size so
the bad block marker (BBM) can be guaranteed located in data chunk. The
ECC layout always using the unbalanced layout(Ecc for both meta and
Data0 chunk), but for the NAND chips with oob larger than 1k, the driver
cannot support because BCH doesn’t support GF 15 for 2K chunk.The change keeps the data chunk no larger than 1k and adjust the ECC
strength or ECC layout to locate the BBM in data chunk. General idea for
large oob NAND chips is1.Try all ECC strength from the minimum value required by NAND spec to
the maximum one that works, any ECC makes the BBM locate in data chunk
can be chosen.2.If none of them works, using separate ECC for meta, which will add one
extra ecc with the same ECC strength as other data chunks. This extra
ECC can guarantee BBM located in data chunk, of course, we need to check
if oob can afford it.Previous code has two methods for ECC layout setting, the
legacy_set_geometry and set_geometry_by_ecc_info, the difference
between these two methods is, legacy_set_geometry set the chunk size
larger chan oob size and then set the maximum ECC strength that oob can
afford. While the set_geometry_by_ecc_info set chunk size and ECC
strength according to NAND spec. It has been proved that the first
method cannot provide safe ECC strength for some modern NAND chips, so
in current code,1. Driver read NAND parameters first and then chose the proper ECC
layout setting method.2. If the oob is large or NAND required data chunk larger than oob size,
chose set_geometry_for_large_oob, otherwise use set_geometry_by_ecc_info3. legacy_set_geometry only used for some NAND chips does not contains
necessary information. So this is only a backup plan, it is NOT
recommended to use these NAND chips.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
save the bch layout setting in debugfs for the upper layer applications,
such as kobs-ng.Signed-off-by: Han Xu
(cherry picked from commit 8a373e796c21f4e9b714039e5f0b7d9388ef5a32)
Signed-off-by: Vipul Kumar -
i.MX6UL also has the DEBUG1 register which can be used for bitflip
detection for erased page.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
The LPSR turns off the power for IOMUX when suspending so restore the
IOMUX when resuming in GPMI NAND driver.The function was not tested yet since NAND only supported on 19x19
LPDDR board.Signed-off-by: Han Xu
Signed-off-by: Fugang Duan
(cherry picked from commit: b0375f42a27044667082e53449e534b265d7a029)Signed-off-by: Vipul Kumar
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support runtime PM on gpmi nand to save the cost to enable/disable clock
in each NAND IO. The driver also claim high-freq bus when resumed.Signed-off-by: Han Xu
In v4.19, some code of drivers/mtd/nand/raw/gpmi-nand/gpmi-lib.c was
removed.commit:
76e1a0086a0c mtd: rawnand: gpmi: support ->setup_data_interface()
b1206122069a mtd: rawnand: gpmi: use core timings instead of an empirical derivationSigned-off-by: Vipul Kumar
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The per1_bch was moved in patch below since it was never mentioned in
any GPMI/BCH/APBH documents, but actually it is necessary for BCH module
since BCH use AXI bus transfer data through fabric, need to enable this
clock for BCH at fabric side.This patch enabled this clock for all i.MX6 platforms and has been
tested on i.MX6Q/i.MX6QP/i.MX6SX and i.MX6UL.commit 9aa0fb0a606a583e2b6e19892ac2cab1b0e726c4
Author: Han Xu
Date: Thu May 28 16:49:18 2015 -0500mtd: nand: support NAND on i.MX6UL
support i.MX6UL GPMI NAND driver and removed the unnecessary clock
per1_bch.Signed-off-by: Han Xu
Fixed in 4.14 rebase for different clock array.
Signed-off-by: Leonard Crestez
Signed-off-by: Vipul Kumar -
support i.MX6UL GPMI NAND driver and removed the unnecessary clock
per1_bch.Signed-off-by: Han Xu
During 4.14 rebase fixed for upstream moving clocks to gpmi_devdata
Signed-off-by: Leonard Crestez
Signed-off-by: Vipul Kumar -
when the maximum ecc NAND oob can afford exceed the ecc strength
controller can provide, use the maximum ecc strength controller can
support instead of the minimum ecc NAND spec required.kobs-ng will also use the same ecc strength to align with kernel to make
sure all NAND chips can boot.Signed-off-by: Han Xu
(cherry picked from commit: 958a2c5b07524f3502cfdefe66724a9a1f8ad608)Signed-off-by: Vipul Kumar
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i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.Signed-off-by: Han Xu
Modified during 4.14 rebase to use GPMI_IS_MX7D instead of GPMI_IS_MX7
because upstream never added GPMI_IS_MX7 when adding mx7 support.Signed-off-by: Leonard Crestez
In v4.19, raw NAND related code moved to the raw/ subdirectory.
Signed-off-by: Vipul Kumar
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for 6UL/7D, the TDH bit should only be set when DDR mode enabled. This
bit cannot be cleared during module reset, so check this bit in
nor_setup to make sure it cleard and won't affect the following
operations.Signed-off-by: Han Xu
(cherry picked from commit 60c6bff99bb07f4bd8975f458dacf1bfb4e967a8)
Signed-off-by: Vipul Kumar -
runtime pm suspend should be called in error path during fsl-quadspi
driver probe. change the code to handle it properly.Add one more hwcaps SNOR_HWCAPS_READ_1_1_4 for the Spansion QSPI nor
s25fl128s since it only indicate this mode as the best performance mode
in SFDP table.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
move the runtime pm get/put functions from nor_setup/nor_setup_last to
probe function to avoid runtime pm re-entrance issue.Signed-off-by: Han Xu
Signed-off-by: Vipul Kumar -
decrese the AHB buffer size for AHB read as a workaround for random
UBIFS data corruptionSigned-off-by: Han Xu
Signed-off-by: Vipul Kumar -
enable runtime suspend/resume for quadspi controller
Signed-off-by: Han Xu
(Vipul: Fixed merge conflicts)
Signed-off-by: Vipul Kumar
