06 Jul, 2022
1 commit
-
Export of_clk_bulk_get_all, so drivers could use this API.
Signed-off-by: Peng Fan
Reviewed-by: Jacky Bai
23 Feb, 2021
1 commit
-
Pull clk updates from Stephen Boyd:
"This is all driver updates, the majority of which is a bunch of new
Qualcomm clk drivers that dominate the diffstat because we add support
for six SoCs from that particular vendor.The other big change is the removal of various clk drivers that are no
longer used now that the kernel is dropping support for those SoCs.Beyond that there's the usual non-critical fixes for existing drivers
and a good number of patches from Lee Jones that cleanup a bunch of
W=1 enabled builds.Removed Drivers:
- Remove efm32 clk driver
- Remove tango4 clk driver
- Remove zte zx clk driver
- Remove sirf prima2/atlast clk drivers
- Remove u300 clk driverNew Drivers:
- PLL support on MStar/SigmaStar ARMv7 SoCs
- CPU clks for Qualcomm SDX55
- GCC and RPMh clks for Qualcomm SC8180x and SC7280 SoCs
- GCC clks for Qualcomm SM8350
- GPU clks for Qualcomm SDM660/SDM630Updates:
- Video clk fixups on Qualcomm SM8250
- Improvements for multimedia clks on Qualcomm MSM8998
- Fix many warnings with W=1 enabled builds under drivers/clk/
- Support crystal load capacitance for Versaclock VC5
- Add a "skip recall" DT binding for Silicon Labs' si570 to avoid
glitches at boot
- Convert Xilinx VCU clk driver to a proper clk provider driver
- Expose Xilinx ZynqMP clk driver to more platforms
- Amlogic pll driver fixup
- Amlogic meson8b clock controller dt support clean up
- Remove mipi clk from the Amlogic axg clock controller
- New Rockchip rk3368 clock ids related to camera input
- Use pr_notice() instead of pr_warn() on i.MX6Q pre-boot ldb_di_clk
reparenting
- A series from Liu Ying that adds some SCU clocks support for
i.MX8qxp DC0/MIPI-LVDS subsystems
- A series from Lucas Stach that adds PLL monitor clocks for i.MX8MQ,
and clkout1/2 support for i.MX8MM/MN
- Add I2c and Ethernet (RAVB) clocks on Renesas R-Car V3U
- Add timer (TMU) clocks on most Renesas R-Car Gen3 SoCs
- Add video-related (FCPVD/VSPD/VSPX), watchdog (RWDT), serial
(HSCIF), pincontrol/GPIO (PFC/GPIO), SPI (MSIOF), SDHI, and DMA
(SYS-DMAC) clocks on Renesas R-Car V3U
- Add support for the USB 2.0 clock selector on Renesas RZ/G2 SoCs
- Allwinner H616 SoC clk support"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (171 commits)
clk: mstar: msc313-mpll: Fix format specifier
clk: mstar: Allow MStar clk drivers to be compile tested
clk: qoriq: use macros to generate pll_mask
clk: qcom: Add Global Clock controller (GCC) driver for SC7280
dt-bindings: clock: Add SC7280 GCC clock binding
clk: qcom: rpmh: Add support for RPMH clocks on SC7280
dt-bindings: clock: Add RPMHCC bindings for SC7280
clk: qcom: gcc-sm8350: add gdsc
dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings
clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver
clk: qcom: mmcc-msm8996: Migrate gfx3d clock to clk_rcg2_gfx3d
clk: qcom: rcg2: Stop hardcoding gfx3d pingpong parent numbers
dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc
clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver
clk: qcom: gcc-sdm660: Mark GPU CFG AHB clock as critical
clk: qcom: gcc-sdm660: Mark MMSS NoC CFG AHB clock as critical
clk: qcom: gpucc-msm8998: Allow fabia gpupll0 rate setting
clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc
clk: qcom: gdsc: Implement NO_RET_PERIPH flag
clk: mstar: MStar/SigmaStar MPLL driver
...
28 Jan, 2021
1 commit
-
The clock API splits its interface into sleepable ant atomic contexts:
- clk_prepare/clk_unprepare for stuff that might sleep
- clk_enable_clk_disable for anything that may be done in atomic context
The code handling runtime PM for clocks only calls clk_disable() on
suspend requests, and clk_enable on resume requests. This means that
runtime PM with clock providers that only have the prepare/unprepare
methods implemented is basically useless.Many clock implementations can't accommodate atomic contexts. This is
often the case when communication with the clock happens through another
subsystem like I2C or SCMI.Let's make the clock PM code useful with such clocks by safely invoking
clk_prepare/clk_unprepare upon resume/suspend requests. Of course, when
such clocks are registered with the PM layer then pm_runtime_irq_safe()
can't be used, and neither pm_runtime_suspend() nor pm_runtime_resume()
may be invoked in atomic context.For clocks that do implement the enable and disable methods then
everything just works as before.A note on sparse:
According to https://lwn.net/Articles/109066/ there are things
that sparse can't cope with. In particular, pm_clk_op_lock() and
pm_clk_op_unlock() may or may not lock/unlock psd->lock depending on
some runtime condition. To work around that we tell it the lock is
always untaken for the purpose of static analisys.Thanks to Naresh Kamboju for reporting issues with the initial patch.
Signed-off-by: Nicolas Pitre
Tested-by: Naresh Kamboju
Signed-off-by: Rafael J. Wysocki
13 Jan, 2021
1 commit
-
Fix kernel-doc notation for 2 functions so that the generated
html is correct. Currently it skips all text between the
':' and the '-', so "[un]register a clock rate" is missing.Fixes: 86bcfa2e87c4 ("clk: add pr_debug & kerneldoc around clk notifiers")
Signed-off-by: Randy Dunlap
Cc: Mike Turquette
Cc: Russell King
Cc: linux-clk@vger.kernel.org
Link: https://lore.kernel.org/r/20210107023304.24442-1-rdunlap@infradead.org
Signed-off-by: Stephen Boyd
21 Dec, 2020
1 commit
-
…d 'clk-samsung' into clk-next
- Camera clks on Qualcomm SC7180 SoCs
- GCC and RPMh clks on Qualcomm SDX55 SoCs
- RPMh clks on Qualcomm SM8350 SoCs
- LPASS clks on Qualcomm SM8250 SoCs
- Add devm variant of clk_notifier_register()
- Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw* clk-doc:
clk: fix a kernel-doc markup* clk-qcom: (27 commits)
clk: qcom: rpmh: add support for SM8350 rpmh clocks
dt-bindings: clock: Add RPMHCC bindings for SM8350
clk: qcom: lpasscc: Introduce pm autosuspend for SC7180
clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2
clk: qcom: gcc-sc7180: Use floor ops for sdcc clks
clk: qcom: Add GDSC support for SDX55 GCC
dt-bindings: clock: Add GDSC in SDX55 GCC
clk: qcom: Add support for SDX55 RPMh clocks
dt-bindings: clock: Introduce RPMHCC bindings for SDX55
clk: qcom: Add SDX55 GCC support
dt-bindings: clock: Add SDX55 GCC clock bindings
clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"
clk: qcom: rpmh: Add CE clock on sdm845.
dt-bindings: clock: Add entry for crypto engine RPMH clock resource
clk: qcom: dispcc-sm8250: handle MMCX power domain
clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones
clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init()
clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks
clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks
dt-bindings: clock: Add support for LPASS Always ON Controller
...* clk-simplify:
clk: remove unneeded dead-store initialization* clk-hw:
clk: meson: g12: use devm variant to register notifiers
clk: add devm variant of clk_notifier_register
clk: meson: g12: drop use of __clk_lookup()
clk: add api to get clk consumer from clk_hw
clk: avoid devm_clk_release name clash* clk-renesas:
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema
clk: renesas: sh73a0: Stop using __raw_*() I/O accessors
clk: renesas: r8a774c0: Add RPC clocks
clk: renesas: r8a779a0: Fix R and OSC clocks
clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv
clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()
clk: renesas: r8a774b1: Add RPC clocks
clk: renesas: r8a774a1: Add RPC clocks
clk: renesas: r8a779a0: Add VIN clocks
clk: renesas: r8a779a0: Add CSI4[0-3] clocks
MAINTAINERS: Update git repo for Renesas clock drivers
clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static
clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI* clk-samsung:
clk: samsung: Prevent potential endless loop in the PLL ops
clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
15 Nov, 2020
2 commits
-
Until now, nothing was done to unregister the dvfs clock notifiers of the
Amlogic g12 SoC family. This is not great but this driver was not really
expected to be unloaded. With the ongoing effort to build everything as
module for this platform, this needs to be cleanly handled.Signed-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20201021163847.595189-3-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd -
Add a memory managed variant of clk_notifier_register() to make life easier
on clock consumers using notifiersSigned-off-by: Jerome Brunet
Link: https://lore.kernel.org/r/20201021163847.595189-2-jbrunet@baylibre.com
Signed-off-by: Stephen Boyd
05 Nov, 2020
1 commit
-
clk_get_duty_cycle -> clk_get_scaled_duty_cycle
Signed-off-by: Mauro Carvalho Chehab
Link: https://lore.kernel.org/r/b2336f3f3cdfe6e1a2d3a7a056ab7ccc7a81b945.1603469755.git.mchehab+huawei@kernel.org
Signed-off-by: Stephen Boyd
07 Jan, 2020
1 commit
-
clk_set_rate() currently starts updating the rate for a clock at the
top-most affected clock and then walks down the tree to update the
bottom-most affected clock last.
This behavior is important for protected clocks where we can switch
between multiple parents to achieve the same output.An example for this is the mali clock tree on Amlogic SoCs:
mali_0_mux (must not change when enabled)
mali_0_div (must not change when enabled)
mali_0 (gate)
mali_1_mux (must not change when enabled)
mali_1_div (must not change when enabled)
mali_1 (gate)
The final output can either use mali_0_gate or mali_1. To change the
final output we must switch to the "inactive" tree. Assuming mali_0 is
active, then we need to prepare mali_1 with the new desired rate and
finally switch the output to the mali_1 tree. This process will then
protect the mali_1 tree and at the same time unprotect the mali_0 tree.
The next call to clk_set_rate() will then switch from the mali_1 tree
back to mali_0.Acked-by: Stephen Boyd
Signed-off-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
21 Sep, 2019
1 commit
-
Pull clk updates from Stephen Boyd:
"We have a small collection of core framework updates this time, mostly
around clk registration by clk providers and debugfs "nice to haves"
for rate constraints. I'll highlight that we're now setting the
clk_init_data pointer inside struct clk_hw to NULL during
clk_register(), which may break some drivers that thought they could
use that pointer during normal operations. That change has been
sitting in next for a while now but maybe something is still broken.
We'l see. Other than that the core framework changes aren't invasive
and they're fixing bugs, simplifying, and making things better.On the clk driver side we got the usual addition of new SoC support,
new features for existing drivers, and bug fixes scattered throughout.
The biggest diffstat is the Amlogic driver that gained CPU clk support
in addition to migrating to the new way of specifying clk parents.
After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
support for various new SoCs and clock controllers from those vendors.Core:
- Drop NULL checks in clk debugfs
- Add min/max rates to clk debugfs
- Set clk_init_data pointer inside clk_hw to NULL after registration
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names
- Evict parents from parent cache when they're unregisteredNew Drivers:
- Add clock driver for i.MX8MN SoCs
- Support aspeed AST2600 SoCs
- Support for Mediatek MT6779 SoCs
- Support qcom SM8150 GCC and RPMh clks
- Support qcom QCS404 WCSS clks
- Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
- Addition of clock driver for Rockchip rk3308 SoCsUpdates:
- Add regulator support to the cdce925 clk driver
- Add support for Raspberry Pi 4 bcm2711 SoCs
- Add SDIO gate support to aspeed driver
- Add missing of_node_put() calls in various clk drivers
- Migrate Amlogic driver to new clock parent description method
- Add DVFS support to Amlogic Meson g12
- Add Amlogic Meson g12a reset support to the axg audio clock controller
- Add sm1 support to the Amlogic Meson g12a clock controller
- Switch i.MX8MM clock driver to platform driver
- Add Hifi4 DSP related clocks for i.MX8QXP SoC
- Fix Audio PLL setting and parent clock for USB
- Misc i.MX8 clock driver improvements and corrections
- Set floor ops for Qualcomm SD clks so that rounding works
- Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
- Enable the Allwinner V3 SoC and fix the i2s clock for H6"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
clk: Drop !clk checks in debugfs dumping
clk: imx: imx8mn: fix pll mux bit
clk: imx: imx8mm: fix pll mux bit
clk: imx: clk-pll14xx: unbypass PLL by default
clk: imx: pll14xx: avoid glitch when set rate
clk: mvebu: ap80x: add AP807 clock support
clk: mvebu: ap806: Prepare the introduction of AP807 clock support
clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
clk: mvebu: ap806: be more explicit on what SaR is
clk: mvebu: ap80x-cpu: add AP807 CPU clock support
clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
dt-bindings: ap806: Document AP807 clock compatible
dt-bindings: ap80x: Document AP807 CPU clock compatible
clk: sprd: add missing kfree
clk: at91: allow 24 Mhz clock as input for PLL
clk: Make clk_bulk_get_all() return a valid "id"
clk: actions: Fix factor clk struct member access
clk: qcom: rcg: Return failure for RCG update
clk: remove extra ---help--- tags in Kconfig
clk: add include guard to clk-conf.h
...
08 Aug, 2019
1 commit
-
The following functions:
- clk_bulk_enable()
- clk_bulk_prepare()
- clk_bulk_disable()
- clk_bulk_unprepare()already expect const clk_bulk_data * as a second parameter, however
their no-op version have mismatching prototypes that don't. Fix that.While at it, constify the second argument of clk_bulk_prepare_enable()
and clk_bulk_disable_unprepare(), since the functions they are
comprised of already accept const clk_bulk_data *.Signed-off-by: Andrey Smirnov
Cc: Russell King
Cc: Stephen Boyd
Cc: Chris Healy
Cc: linux-clk@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Link: https://lkml.kernel.org/r/20190717145651.17250-1-andrew.smirnov@gmail.com
Signed-off-by: Stephen Boyd
23 Jul, 2019
1 commit
-
Fix an incomplete devm_clk_bulk_get_optional() function documentation
by adding description of the num_clks argument as in other *clk_bulk*
functions.Fixes: 9bd5ef0bd874 ("clk: Add devm_clk_bulk_get_optional() function")
Reported-by: kbuild test robot
Signed-off-by: Sylwester Nawrocki
Signed-off-by: Stephen Boyd
18 Jul, 2019
1 commit
-
Pull clk updates from Stephen Boyd:
"This round of clk driver and framework updates is heavy on the driver
update side. The two main highlights in the core framework are the
addition of an bulk clk_get API that handles optional clks and an
extra debugfs file that tells the developer about the current parent
of a clk.The driver updates are dominated by i.MX in the diffstat, but that is
mostly because that SoC has started converting to the clk_hw style of
clk registration. The next big update is in the Amlogic meson clk
driver that gained some support for audio, cpu, and temperature clks
while fixing some PLL issues. Finally, the biggest thing that stands
out is the conversion of a large part of the Allwinner sunxi-ng driver
to the new clk parent scheme that uses less strings and more pointer
comparisons to match clk parents and children up.In general, it looks like we have a lot of little fixes and tweaks
here and there to clk data along with the normal addition of a handful
of new drivers and a couple new core framework features.Core:
- Add a 'clk_parent' file in clk debugfs
- Add a clk_bulk_get_optional() API (with devm too)New Drivers:
- Support gated clk controller on MIPS based BCM63XX SoCs
- Support SiLabs Si5341 and Si5340 chips
- Support for CPU clks on Raspberry Pi devices
- Audsys clock driver for MediaTek MT8516 SoCsUpdates:
- Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
- Small frequency support for SiLabs Si544 chips
- Slow clk support for AT91 SAM9X60 SoCs
- Remove dead code in various clk drivers (-Wunused)
- Support for Marvell 98DX1135 SoCs
- Get duty cycle of generic pwm clks
- Improvement in mmc phase calculation and cleanup of some rate defintions
- Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
- Add GPIO, SNVS and GIC clocks for i.MX8 drivers
- Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
- Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
- Add clks for new Exynos5422 Dynamic Memory Controller driver
- Clock definition for Exynos4412 Mali
- Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
- Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
- TI clock probing done from DT by default instead of firmware
- Fix Amlogic Meson mpll fractional part and spread sprectrum issues
- Add Amlogic meson8 audio clocks
- Add Amlogic g12a temperature sensors clocks
- Add Amlogic g12a and g12b cpu clocks
- Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
- Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
- Add Clock Domain support on Renesas RZ/N1"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
clk: consoldiate the __clk_get_hw() declarations
clk: sprd: Add check for return value of sprd_clk_regmap_init()
clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
clk: Add Si5341/Si5340 driver
dt-bindings: clock: Add silabs,si5341
clk: clk-si544: Implement small frequency change support
clk: add BCM63XX gated clock controller driver
devicetree: document the BCM63XX gated clock bindings
clk: at91: sckc: use dedicated functions to unregister clock
clk: at91: sckc: improve error path for sama5d4 sck registration
clk: at91: sckc: remove unnecessary line
clk: at91: sckc: improve error path for sam9x5 sck register
clk: at91: sckc: add support to free slow clock osclillator
clk: at91: sckc: add support to free slow rc oscillator
clk: at91: sckc: add support to free slow oscillator
clk: rockchip: export HDMIPHY clock on rk3228
clk: rockchip: add watchdog pclk on rk3328
clk: rockchip: add clock id for hdmi_phy special clock on rk3228
clk: rockchip: add clock id for watchdog pclk on rk3328
clk: at91: sckc: add support for SAM9X60
...
26 Jun, 2019
2 commits
-
Add managed version of the clk_bulk_get_optional() helper function.
Signed-off-by: Sylwester Nawrocki
[sboyd@kernel.org: Mark __devm_clk_bulk_get() static]
Signed-off-by: Stephen Boyd -
clk_bulk_get_optional() allows to get a group of clocks where one
or more is optional. For a not available clock, e.g. not specifed
in the clock consumer node in DT, its respective struct clk pointer
will be NULL. This allows for operating on a group of returned
clocks (struct clk_bulk_data array) with existing clk_bulk* APIs.Signed-off-by: Sylwester Nawrocki
Signed-off-by: Stephen Boyd
19 Jun, 2019
1 commit
-
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundationthis program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner
Reviewed-by: Enrico Weigelt
Reviewed-by: Kate Stewart
Reviewed-by: Allison Randal
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman
25 Apr, 2019
1 commit
-
Compilation fails if any of undeclared clk_set_*() functions are in use
and CONFIG_HAVE_CLK=n.Reported-by: kbuild test robot
Signed-off-by: Dmitry Osipenko
Signed-off-by: Stephen Boyd
07 Feb, 2019
1 commit
-
This adds clk_get_optional() and devm_clk_get_optional() functions to get
optional clocks.They behave the same as (devm_)clk_get() except where there is no clock
producer. In this case, instead of returning -ENOENT, the function
returns NULL. This makes error checking simpler and allows
clk_prepare_enable, etc to be called on the returned reference
without additional checks.Signed-off-by: Phil Edworthy
Reviewed-by: Andy Shevchenko
Cc: Russell King
[sboyd@kernel.org: Document in devres.txt]
Signed-off-by: Stephen Boyd
19 Oct, 2018
1 commit
-
- Nvidia Tegra clk driver MBIST workaround fix
- clk_bulk_get_all() API and friends to get all the clks for a device* clk-tegra:
clk: tegra210: Include size.h for compilation ease
clk: tegra: Fixes for MBIST work around
clk: tegra: probe deferral error reporting* clk-bulk-get-all:
clk: add managed version of clk_bulk_get_all
clk: add new APIs to operate on all available clocks
clk: bulk: add of_clk_bulk_get()
17 Oct, 2018
2 commits
-
This patch introduces the managed version of clk_bulk_get_all.
Cc: Michael Turquette
Cc: Stephen Boyd
Tested-by: Thor Thayer
Signed-off-by: Dong Aisheng
Signed-off-by: Stephen Boyd -
This patch introduces of_clk_bulk_get_all and clk_bulk_x_all APIs
to users who just want to handle all available clocks from device tree
without need to know the detailed clock information likes clock numbers
and names. This is useful in writing some generic drivers to handle clock
part.Cc: Stephen Boyd
Cc: Masahiro Yamada
Tested-by: Thor Thayer
Signed-off-by: Dong Aisheng
Signed-off-by: Stephen Boyd
03 Oct, 2018
1 commit
-
Deep enough power saving mode can result into losing context of the clock
registers also, and they need to be restored once coming back from the power
saving mode. Hence add functions to save/restore clock context.Signed-off-by: Keerthy
Signed-off-by: Russ Dill
Acked-by: Tony Lindgren
Signed-off-by: Tero Kristo
20 Jun, 2018
1 commit
-
Add the possibility to apply and query the clock signal duty cycle ratio.
This is useful when the duty cycle of the clock signal depends on some
other parameters controlled by the clock framework.For example, the duty cycle of a divider may depends on the raw divider
setting (ratio = N / div) , which is controlled by the CCF. In such case,
going through the pwm framework to control the duty cycle ratio of this
clock would be a burden.A clock provider is not required to implement the operation to set and get
the duty cycle. If it does not implement .get_duty_cycle(), the ratio is
assumed to be 50%.This change also adds a new flag, CLK_DUTY_CYCLE_PARENT. This flag should
be used to indicate that a clock, such as gates and muxes, may inherit
the duty cycle ratio of its parent clock. If a clock does not provide a
get_duty_cycle() callback and has CLK_DUTY_CYCLE_PARENT, then the call
will be directly forwarded to its parent clock, if any. For
set_duty_cycle(), the clock should also have CLK_SET_RATE_PARENT for the
call to be forwardedSigned-off-by: Jerome Brunet
Signed-off-by: Michael Turquette
Link: lkml.kernel.org/r/20180619144141.8506-1-jbrunet@baylibre.com
17 Mar, 2018
1 commit
-
we need it even when !CONFIG_HAVE_CLK because it allows
us to catch missing checking return values in the non-clk
compile configurations too. More test coverage.Cc: Stephen Boyd
Suggested-by: Stephen Boyd
Signed-off-by: Dong Aisheng
Signed-off-by: Stephen Boyd
20 Dec, 2017
1 commit
-
Using clock rate protection, we can now provide a way for clock consumer
to claim exclusive control over the rate of a producerSo far, rate change operations have been a "last write wins" affair. This
changes allows drivers to explicitly protect against this behavior, if
required.Of course, if exclusivity over a producer is claimed more than once, the
rate is effectively locked as exclusivity cannot be preemptedTested-by: Maxime Ripard
Acked-by: Michael Turquette
Signed-off-by: Jerome Brunet
Signed-off-by: Michael Turquette
Link: lkml.kernel.org/r/20171201215200.23523-10-jbrunet@baylibre.com
15 Jul, 2017
1 commit
-
Pull clk api update from Stephen Boyd:
"Small patch to add the clk_bulk_prepare_enable() and
clk_bulk_disable_unprepare() API to the newly introduced
clk bulk APIs.It would be good to get this into the -rc1 so that other
driver trees can use it for code targeted for the next
merge window"* tag 'clk-bulk-get-prep-enable' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: Provide bulk prepare_enable disable_unprepare variants
13 Jul, 2017
1 commit
-
This extends the existing set of bulk helpers with prepare_enable and
disable_unprepare variants.Cc: Russell King ,
Cc: Dong Aisheng
Signed-off-by: Bjorn Andersson
Signed-off-by: Stephen Boyd
03 Jun, 2017
4 commits
-
* clk-bulk-get:
clk: add managed version of clk_bulk_get
clk: add clk_bulk_get accessories -
This patch introduces the managed version of clk_bulk_get.
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Russell King
Cc: Geert Uytterhoeven
Cc: "Rafael J. Wysocki"
Cc: Viresh Kumar
Cc: Mark Brown
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Sascha Hauer
Cc: Anson Huang
Cc: Robin Gong
Cc: Bai Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
Signed-off-by: Stephen Boyd -
These helper function allows drivers to get several clk consumers in
one operation. If any of the clk cannot be acquired then any clks
that were got will be put before returning to the caller.This can relieve the driver owners' life who needs to handle many clocks,
as well as each clock error reporting.Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Russell King
Cc: Geert Uytterhoeven
Cc: "Rafael J. Wysocki"
Cc: Viresh Kumar
Cc: Mark Brown
Cc: Shawn Guo
Cc: Fabio Estevam
Cc: Sascha Hauer
Cc: Anson Huang
Cc: Robin Gong
Cc: Bai Ping
Cc: Leonard Crestez
Cc: Octavian Purdila
Signed-off-by: Dong Aisheng
Signed-off-by: Stephen Boyd -
When CONFIG_ON=n, dummies are provided for of_clk_get() and
of_clk_get_by_name(), but not for of_clk_get_from_provider().Provide a dummy for the latter, to improve the ability to do
compile-testing. This requires removing the existing dummy in the
Lantiq clock code.Fixes: 766e6a4ec602d0c1 ("clk: add DT clock binding support")
Signed-off-by: Geert Uytterhoeven
Acked-by: Thomas Langer
Signed-off-by: Stephen Boyd
03 Apr, 2017
1 commit
-
./lib/string.c:134: WARNING: Inline emphasis start-string without end-string.
./mm/filemap.c:522: WARNING: Inline interpreted text or phrase reference start-string without end-string.
./mm/filemap.c:1283: ERROR: Unexpected indentation.
./mm/filemap.c:3003: WARNING: Inline interpreted text or phrase reference start-string without end-string.
./mm/vmalloc.c:1544: WARNING: Inline emphasis start-string without end-string.
./mm/page_alloc.c:4245: ERROR: Unexpected indentation.
./ipc/util.c:676: ERROR: Unexpected indentation.
./drivers/pci/irq.c:35: WARNING: Block quote ends without a blank line; unexpected unindent.
./security/security.c:109: ERROR: Unexpected indentation.
./security/security.c:110: WARNING: Definition list ends without a blank line; unexpected unindent.
./block/genhd.c:275: WARNING: Inline strong start-string without end-string.
./block/genhd.c:283: WARNING: Inline strong start-string without end-string.
./include/linux/clk.h:134: WARNING: Inline emphasis start-string without end-string.
./include/linux/clk.h:134: WARNING: Inline emphasis start-string without end-string.
./ipc/util.c:477: ERROR: Unknown target name: "s".Signed-off-by: Mauro Carvalho Chehab
Acked-by: Bjorn Helgaas
Signed-off-by: Jonathan Corbet
09 Dec, 2016
1 commit
-
Some driver is using this type of DT bindings for clock (more detail,
see ${LINUX}/Documentation/devicetree/bindings/sound/simple-card.txt).sound_soc {
...
cpu {
clocks = ;
...
};
codec {
clocks = ;
...
};
};Current driver in this case uses of_clk_get() for each node, but there
is no devm_of_clk_get() today.
OTOH, the problem of having devm_of_clk_get() is that it encourages the
use of of_clk_get() when clk_get() is more desirable.Thus, this patch adds new devm_get_clk_from_chile() which explicitly
reads as get a clock from a child node of this device.
By this function, we can also use this type of DT bindingssound_soc {
clocks = , ;
clock-names = "cpu", "codec";
clock-ranges;
...
cpu {
...
};
codec {
...
};
};Signed-off-by: Kuninori Morimoto
[sboyd@codeurora.org: Rename subject to clk + add API]
Signed-off-by: Stephen Boyd
31 Jul, 2016
1 commit
-
Pull clk updates from Michael Turquette:
"The bulk of the changes are updates and fixes to existing clk provider
drivers, along with a pretty standard number of new drivers. The core
recieved a small number of updates as well.Core changes of note:
- removed CLK_IS_ROOT flagNew clk provider drivers:
- Renesas r8a7796 clock pulse generator / module standby and
software reset
- Allwinner sun8i H3 clock controller unit
- AmLogic meson8b clock controller (rewritten)
- AmLogic gxbb clock controller
- support for some new ICs was added by simple changes to static
data tables for chips sharing the same familyDriver updates of note:
- the Allwinner sunxi clock driver infrastucture was rewritten to
comform to the state of the art at drivers/clk/sunxi-ng. The old
implementation is still supported for backwards compatibility with
the DT ABI"* tag 'clk-for-linus-4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (162 commits)
clk: Makefile: re-sort and clean up
Revert "clk: gxbb: expose CLKID_MMC_PCLK"
clk: samsung: Allow modular build of the Audio Subsystem CLKCON driver
clk: samsung: make clk-s5pv210-audss explicitly non-modular
clk: exynos5433: remove CLK_IGNORE_UNUSED flag from SPI clocks
clk: oxnas: Add hardware dependencies
clk: imx7d: do not set parent of ethernet time/ref clocks
ARM: dt: sun8i: switch the H3 to the new CCU driver
clk: sunxi-ng: h3: Fix Kconfig symbol typo
clk: sunxi-ng: h3: Fix audio clock divider offset
clk: sunxi-ng: Add H3 clocks
clk: sunxi-ng: Add N-K-M-P factor clock
clk: sunxi-ng: Add N-K-M Factor clock
clk: sunxi-ng: Add N-M-factor clock support
clk: sunxi-ng: Add N-K-factor clock support
clk: sunxi-ng: Add M-P factor clock support
clk: sunxi-ng: Add divider
clk: sunxi-ng: Add phase clock support
clk: sunxi-ng: Add mux clock support
clk: sunxi-ng: Add gate clock support
...
29 Jun, 2016
1 commit
-
The clk notifier symbols are hidden by COMMON_CLK. However on some
platforms HAVE_CLK might be set while COMMON_CLK not which leads to
compile test build errors like:$ make.cross ARCH=sh
drivers/devfreq/tegra-devfreq.c: In function 'tegra_actmon_rate_notify_cb':
>> drivers/devfreq/tegra-devfreq.c:391:16: error: 'POST_RATE_CHANGE' undeclared (first use in this function)
if (action != POST_RATE_CHANGE)
^
drivers/devfreq/tegra-devfreq.c: In function 'tegra_devfreq_probe':
>> drivers/devfreq/tegra-devfreq.c:654:8: error: implicit declaration of function 'clk_notifier_register' [-Werror=implicit-function-declaration]
err = clk_notifier_register(tegra->emc_clock, &tegra->rate_change_nb);
^Export the macros and data type declarations outside of COMMON_CLK ifdef
and provide stubs to fix the compile testing.Reported-by: kbuild test robot
Signed-off-by: Krzysztof Kozlowski
Tested-by: Bartlomiej Zolnierkiewicz
Signed-off-by: Stephen Boyd
28 Jun, 2016
1 commit
-
When compiling with the COMPILE_TEST option set, the clps711x does not
compile because of the clk_get_sys() noop stub missing.Signed-off-by: Daniel Lezcano
Reviewed-by: Michael Turquette
06 May, 2015
2 commits
-
clk_add_alias() is provided by clkdev, and is not part of the clk API.
Howver, it is prototyped in two locations: linux/clkdev.h and
linux/clk.h. This is a mess. Get rid of the redundant and unnecessary
version in linux/clk.h.Acked-by: Tony Lindgren
Tested-by: Robert Jarzmik
Acked-by: Sekhar Nori
Signed-off-by: Russell King -
The idea is that rate = clk_round_rate(clk, r) is equivalent to:
clk_set_rate(clk, r);
rate = clk_get_rate(clk);except that clk_round_rate() does not change the hardware in any way.
Signed-off-by: Russell King
12 Mar, 2015
1 commit
-
Some drivers compare struct clk pointers as a means of knowing
if the two pointers reference the same clock hardware. This behavior is
dubious (drivers must not dereference struct clk), but did not cause any
regressions until the per-user struct clk patch was merged. Now the test
for matching clk's will always fail with per-user struct clk's.clk_is_match is introduced to fix the regression and prevent drivers
from comparing the pointers manually.Fixes: 035a61c314eb ("clk: Make clk API return per-user struct clk instances")
Cc: Russell King
Cc: Shawn Guo
Cc: Tomeu Vizoso
Signed-off-by: Michael Turquette
[arnd@arndb.de: Fix COMMON_CLK=N && HAS_CLK=Y config]
Signed-off-by: Arnd Bergmann
[sboyd@codeaurora.org: const arguments to clk_is_match() and
remove unnecessary ternary operation]
Signed-off-by: Stephen Boyd
03 Feb, 2015
1 commit
-
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.Signed-off-by: Tomeu Vizoso
Signed-off-by: Stephen Boyd
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
migrated clk-private.h changes to clk.c]
