29 Jun, 2011
13 commits
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On pseries machines, consoles are provided by the hypervisor using
a low level get_chars/put_chars type interface. However, this is
really just a transport to the service processor which implements
them either as "raw" console (networked consoles, HMC, ...) or as
"hvsi" serial ports.The later is a simple packet protocol on top of the raw character
interface that is supposed to convey additional "serial port" style
semantics. In practice however, all it does is provide a way to
read the CD line and set/clear our DTR line, that's it.We currently implement the "raw" protocol as an hvc console backend
(/dev/hvcN) and the "hvsi" protocol using a separate tty driver
(/dev/hvsi0).However this is quite impractical. The arbitrary difference between
the two type of devices has been a major source of user (and distro)
confusion. Additionally, there's an additional mini -hvsi implementation
in the pseries platform code for our low level debug console and early
boot kernel messages, which means code duplication, though that low
level variant is impractical as it's incapable of doing the initial
protocol negociation to establish the link to the FSP.This essentially replaces the dedicated hvsi driver and the platform
udbg code completely by extending the existing hvc_vio backend used
in "raw" mode so that:- It now supports HVSI as well
- We add support for hvc backend providing tiocm{get,set}
- It also provides a udbg interface for early debug and boot consoleThis is overall less code, though this will only be obvious once we
remove the old "hvsi" driver, which is still available for now. When
the old driver is enabled, the new code still kicks in for the low
level udbg console, replacing the old mini implementation in the platform
code, it just doesn't provide the higher level "hvc" interface.In addition to producing generally simler code, this has several benefits
over our current situation:- The user/distro only has to deal with /dev/hvcN for the hypervisor
console, avoiding all sort of confusion that has plagued us in the past- The tty, kernel and low level debug console all use the same code
base which supports the full protocol establishment process, thus the
console is now available much earlier than it used to be with the
old HVSI driver. The kernel console works much earlier and udbg is
available much earlier too. Hackers can enable a hard coded very-early
debug console as well that works with HVSI (previously that was only
supported for the "raw" mode).I've tried to keep the same semantics as hvsi relative to how I react
to things like CD changes, with some subtle differences though:- I clear DTR on close if HUPCL is set
- Current hvsi triggers a hangup if it detects a up->down transition
on CD (you can still open a console with CD down). My new implementation
triggers a hangup if the link to the FSP is severed, and severs it upon
detecting a up->down transition on CD.Signed-off-by: Benjamin Herrenschmidt
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When CONFIG_PPC_EARLY_DEBUG is set, call register_early_udbg_console()
early from generic code.Signed-off-by: Benjamin Herrenschmidt
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Embed the struct hvsi_header in the various packet definitions
rather than open coding it multiple times. Will help provide
stronger type checking.Signed-off-by: Benjamin Herrenschmidt
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This moves various HVSI protocol definitions from the hvsi.c
driver to a header file that can be used later on by a udbg
implementationSigned-off-by: Benjamin Herrenschmidt
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Currently Maple setup code creates cpc925_edac device only on
Motorola ATCA-6101 blade. Make setup code check bridge revision
and enable EDAC on all U3H bridges.Verified on Momentum MapleD (ppc970fx kit) board.
Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Benjamin Herrenschmidt -
Reconfiguration notifier call for device node may fail by several reasons,
but it always assumes kmalloc failures.This enables reconfiguration notifier call chain to get the actual error
code rather than -ENOMEM by converting all reconfiguration notifier calls
to return encapsulate error code with notifier_from_errno().Signed-off-by: Akinobu Mita
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Benjamin Herrenschmidt -
This introduces pSeries_reconfig_notify() as a just wrapper of
blocking_notifier_call_chain() for pSeries_reconfig_chain.This is a preparation to improvement of error code on reconfiguration
notifier failure.Signed-off-by: Akinobu Mita
Cc: Benjamin Herrenschmidt
Cc: Paul Mackerras
Cc: linuxppc-dev@lists.ozlabs.org
Signed-off-by: Benjamin Herrenschmidt -
Enable functions used to access SCOM if PPC_MAPLE is defined: they are
used by cpufreq driver to control hardware.Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Benjamin Herrenschmidt -
This has been broken for a while but hasn't been an issue until
now because nobody was reserving regions at high addresses.Signed-off-by: Becky Bruce
Signed-off-by: Benjamin Herrenschmidt -
Signed-off-by: Becky Bruce
Signed-off-by: Benjamin Herrenschmidt -
On MMUs such as FSL where we can guarantee the entire linear mapping is
bolted, we don't need to worry about linear TLB misses. If on top of
that we do a full table walk, we get rid of all recursive TLB faults, and
can dispense with some state saving. This gains a few percent on
TLB-miss-heavy workloads, and around 50% on a benchmark that had a high
rate of virtual page table faults under the normal handler.While touching the EX_TLB layout, remove EX_TLB_MMUCR0, EX_TLB_SRR0, and
EX_TLB_SRR1 as they're not used.[BenH: Fixed build with 64K pages (wsp config)]
Signed-off-by: Scott Wood
Signed-off-by: Benjamin Herrenschmidt -
Signed-off-by: Scott Wood
Signed-off-by: Benjamin Herrenschmidt
28 Jun, 2011
2 commits
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This will allow the new HW RNG driver to bind on these boards
Signed-off-by: Mike Williams
Signed-off-by: Josh Boyer -
The Sequoia board has a Security function IP block on it that contains a TRNG.
Add the crypto and rng portions of that IP block to the DTS.Signed-off-by: Josh Boyer
27 Jun, 2011
19 commits
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The Freescale hypervisor does not allow guests to write to the timebase
registers (virtualizing the timebase register was deemed too complicated),
so don't try to synchronize the timebase registers when we're running
under the hypervisor.This typically happens when kexec support is enabled.
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
P1010RDB Overview
-----------------
1Gbyte DDR3 (on board DDR)
32Mbyte 16bit NOR flash
32Mbyte SLC NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
I2C Board 128x8 bit memory
SD/MMC connector to interface with the SD memory card
2 SATA interface
1 internal SATA connect to 2.5. 160G SATA2 HDD
1 eSATA connector to rear panel
USB 2.0
x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface.
x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet
eTSEC1: Connected to RGMII PHY VSC8641XKO
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY VSC8221 eCAN
Two DB-9 female connectors for Field bus interface UART
DUART interface: supports two UARTs up to 115200 bps for console displaySigned-off-by: Poonam Aggrwal
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala -
Enable framebuffer console support by default in the defconfig on the
Freescale MPC8610 HPCD reference board. This allows the boot messages to
be shown on the video display.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
mpc8610hpcd_set_pixel_clock() calculates the correct value of the PXCLK
bits in the CLKDVDR register for a given pixel clock rate. The code which
performs this calculation is overly complicated and includes an error
estimation routine that doesn't work most of the time anyway. Replace the
code with the simpler routine that's currently used on the P1022DS.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
Enable framebuffer console support by default in the defconfigs for the
Freescale 85xx-based reference board. This allows the boot messages to
be shown on the video display on the P1022DS.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
To ensure that the DIU pixel clock will not be set to an invalid value,
clamp the PXCLK divider to the allowed range (2-255). This also acts as
a limiter for the pixel clock.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
e500mc cannot doze or nap due to an erratum (as well as having a
different mechanism than previous e500), but it has a "wait" instruction
that is similar to doze.On 64-bit, due to the soft-irq-disable mechanism, the existing
book3e_idle should be used instead.Signed-off-by: Vakul Garg
Signed-off-by: Scott Wood
Signed-off-by: Kumar Gala -
Split out common (non-board specific) parts of the SoC related device
tree into a stub so multiple board dts files can include it and we can
reduce duplication and maintenance effort.Signed-off-by: Kumar Gala
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Cc: Kumar Gala
Signed-off-by: Baruch Siach
Signed-off-by: Kumar Gala -
The platform file for the Freecale P1022DS reference board is not freeing
the ioremap() mapping of the PIXIS and global utilities nodes it creates.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
fsl-lbc driver requires an interrupt to bind to localbus device.
Populate 85xx boards' dts trees with lbc interrupt info.Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
Signed-off-by: Dmitry Eremin-Solenikov
Signed-off-by: Kumar Gala -
Signed-off-by: Lei Xu
Signed-off-by: Kumar Gala -
Signed-off-by: Lei Xu
Signed-off-by: Kumar Gala -
FSL PCIe controller can act as agent(EP) or host(RC). Under Agent(EP) mode
the controller will be configured by the host system. So its not required
to be registered with the PCI(e) sub-system. We only register the
controller if its configured in host(RC) mode.Signed-off-by: Vivek Mahajan
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Kumar Gala -
Add support for the ePAPR-compliant Freescale hypervisor (aka "Topaz") on
the Freescale P3041DS, P4080DS, and P5020DS reference boards.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
Add functions to restart and halt the current partition when running under
the Freescale hypervisor. These functions should be assigned to various
function pointers of the ppc_md structure during the .probe() function for
the board:ppc_md.restart = fsl_hv_restart;
ppc_md.power_off = fsl_hv_halt;
ppc_md.halt = fsl_hv_halt;Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
The Freescale ePAPR reference hypervisor provides interrupt controller
services via a hypercall interface, instead of emulating the MPIC
controller. This is called the VMPIC.The ePAPR "virtual interrupt controller" provides interrupt controller
services for external interrupts. External interrupts received by a
partition can come from two sources:- Hardware interrupts - hardware interrupts come from external
interrupt lines or on-chip I/O devices.
- Virtual interrupts - virtual interrupts are generated by the hypervisor
as part of some hypervisor service or hypervisor-created virtual device.Both types of interrupts are processed using the same programming model and
same set of hypercalls.Signed-off-by: Ashish Kalra
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
ePAPR hypervisors provide operating system services via a "hypercall"
interface. The following steps need to be performed to make an hcall:1. Load r11 with the hcall number
2. Load specific other registers with parameters
3. Issue instrucion "sc 1"
4. The return code is in r3
5. Other returned parameters are in other registers.To provide this service to the kernel, these steps are wrapped in inline
assembly functions. Standard ePAPR hcalls are in epapr_hcalls.h, and
Freescale extensions are in fsl_hcalls.h.Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala
23 Jun, 2011
6 commits
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Move irq_choose_cpu() into arch/powerpc/kernel/irq.c so that it can be used
by other PIC drivers. The function is not MPIC-specific.Signed-off-by: Stuart Yoder
Signed-off-by: Timur Tabi
Signed-off-by: Kumar Gala -
Only 32-bit SoCs have a QUICC Engine so limit the config option to PPC32.
Signed-off-by: Kumar Gala
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Signed-off-by: Kumar Gala
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We need the FSL specific header fixup code on both 32-bit and 64-bit
platforms so just move the code into pci-common.c.Signed-off-by: Kumar Gala
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The P1023 processor is an e500v2 based SoC that utilizes the DPAA
networking architecture. This adds basic board support for non-DPAA
functionality (device tree, board file, etc).Signed-off-by: Roy Zang
Signed-off-by: Haiying Wang
Signed-off-by: Kumar Gala -
We expect this is actually faster, and we end up needing more space than we
can get from the SPRGs in some instances. This is also useful when running
as a guest OS - SPRGs4-7 do not have guest versions.8 slots are allocated in thread_info for this even though we only actually
use 4 of them - this allows space for future code to have more scratch
space (and we know we'll need it for things like hugetlb).Signed-off-by: Ashish Kalra
Signed-off-by: Becky Bruce
Signed-off-by: Kumar Gala
