Eric Lee / smarc-fsl-linux-kernel

20 Sep, 2020

1 commit

  • f025d9d99   riscv: Fix Kendryte K210 device tree ... Browse Code »

    The Kendryte K210 SoC CLINT is compatible with Sifive clint v0
    (sifive,clint0). Fix the Kendryte K210 device tree clint entry to be
    inline with the sifive timer definition documented in
    Documentation/devicetree/bindings/timer/sifive,clint.yaml.
    The device tree clint entry is renamed similarly to u-boot device tree
    definition to improve compatibility with u-boot defined device tree.
    To ensure correct initialization, the interrup-cells attribute is added
    and the interrupt-extended attribute definition fixed.

    This fixes boot failures with Kendryte K210 SoC boards.

    Note that the clock referenced is kept as K210_CLK_ACLK, which does not
    necessarilly match the clint MTIME increment rate. This however does not
    seem to cause any problem for now.

    Signed-off-by: Damien Le Moal
    Signed-off-by: Palmer Dabbelt

    Damien Le Moal
     

31 Jul, 2020

1 commit

  • 20d38f7c4   riscv: Allow building with kcov coverage ... Browse Code »

    Add ARCH_HAS_KCOV and HAVE_GCC_PLUGINS to the riscv Kconfig.
    Also disable instrumentation of some early boot code and vdso.

    Boot-tested on QEMU's riscv64 virt machine.

    Signed-off-by: Tobias Klauser
    Acked-by: Dmitry Vyukov
    Signed-off-by: Palmer Dabbelt

    Tobias Klauser
     

19 May, 2020

1 commit

  • 8bb661742   riscv: K210: Add a built-in device tree ... Browse Code »

    The K210's bootloader does not provide a device tree. Give the ability
    to providea builtin one with the SOC_KENDRYTE_K210_BUILTIN_DTB option.
    If selected, this option result in the definition of a builtin DTB
    entry in the k210 sysctl driver.

    If defined, the builtin DTB entry points to the default k210.dts device
    tree file and is keyed with the vendor ID 0x4B5, the arch ID
    0xE59889E6A5A04149 ("Canaan AI" in UTF-8 coded Chinese) and the impl ID
    0x4D41495832303030 ("MAIX200"). These values are reported by the SiPEED
    MAIXDUINO board, the SiPEED MAIX Go board and the SiPEED Dan Dock board.

    [Thanks to Damien for the K210 IDs]
    Signed-off-by: Damien Le Moal
    Signed-off-by: Palmer Dabbelt

    Palmer Dabbelt
     

10 Apr, 2020

1 commit

  • eab400266   Merge tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux ... Browse Code »

    Pull RISC-V updates from Palmer Dabbelt:
    "This contains a handful of new features:

    - Partial support for the Kendryte K210.

    There are still a few outstanding issues that I have patches for,
    but I don't actually have a board to test them so they're not
    included yet.

    - SBI v0.2 support.

    - Fixes to support for building with LLVM-based toolchains. The
    resulting images are known not to boot yet.

    I don't anticipate a part two, but I'll probably have something early
    in the RCs to finish up the K210 support"

    * tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits)
    riscv: create a loader.bin boot image for Kendryte SoC
    riscv: Kendryte K210 default config
    riscv: Add Kendryte K210 device tree
    riscv: Select required drivers for Kendryte SOC
    riscv: Add Kendryte K210 SoC support
    riscv: Add SOC early init support
    riscv: Unaligned load/store handling for M_MODE
    RISC-V: Support cpu hotplug
    RISC-V: Add supported for ordered booting method using HSM
    RISC-V: Add SBI HSM extension definitions
    RISC-V: Export SBI error to linux error mapping function
    RISC-V: Add cpu_ops and modify default booting method
    RISC-V: Move relocate and few other functions out of __init
    RISC-V: Implement new SBI v0.2 extensions
    RISC-V: Introduce a new config for SBI v0.1
    RISC-V: Add SBI v0.2 extension definitions
    RISC-V: Add basic support for SBI v0.2
    RISC-V: Mark existing SBI as 0.1 SBI.
    riscv: Use macro definition instead of magic number
    riscv: Add support to dump the kernel page tables
    ...

    Linus Torvalds
     

04 Apr, 2020

2 commits

  • 37809df4b   riscv: create a loader.bin boot image for Kendryte SoC ... Browse Code »

    Create the loader.bin bootable image file that can be loaded into
    Kendryte K210 based boards using the kflash.py tool with the command:

    kflash.py/kflash.py -t arch/riscv/boot/loader.bin

    Signed-off-by: Christoph Hellwig
    Signed-off-by: Damien Le Moal
    Reviewed-by: Anup Patel
    Reviewed-by: Palmer Dabbelt
    Signed-off-by: Palmer Dabbelt

    Christoph Hellwig
     
  • 5ba568f57   riscv: Add Kendryte K210 device tree ... Browse Code »

    Add a generic device tree for Kendryte K210 SoC based boards. This is
    for now a very simple device tree describing the core elements of the
    SoC. This is suitable (and tested) for the Kendryte KD233 development
    board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.

    Signed-off-by: Damien Le Moal
    Reviewed-by: Sean Anderson
    Signed-off-by: Palmer Dabbelt

    Damien Le Moal
     

25 Mar, 2020

1 commit

06 Mar, 2020

1 commit

20 Feb, 2020

1 commit

29 Jan, 2020

1 commit

03 Jan, 2020

1 commit

09 Dec, 2019

1 commit

  • 0e72a2f9c   riscv: Fix build dependency for loader ... Browse Code »

    The Makefile addition for the flat image loader missed an obj prefix.

    For most parallel builds this worked out fine, but with -j1 the dependency
    wasn't fulfilled and thus fails:

    arch/riscv/boot/loader.S: Assembler messages:
    arch/riscv/boot/loader.S:7: Error: file not found: arch/riscv/boot/Image

    Fixes: 405fe7aa0dba ("riscv: provide a flat image loader")
    Cc: Christoph Hellwig
    Signed-off-by: Olof Johansson
    Reviewed-by: Anup Patel
    Signed-off-by: Paul Walmsley

    Olof Johansson
     

23 Nov, 2019

1 commit

18 Nov, 2019

1 commit

  • 405fe7aa0   riscv: provide a flat image loader ... Browse Code »

    This allows just loading the kernel at a pre-set address without
    qemu going bonkers trying to map the ELF file.

    Contains a contribution from Aurabindo Jayamohanan to reuse the
    PAGE_OFFSET definition.

    Signed-off-by: Christoph Hellwig
    Reviewed-by: Anup Patel
    [paul.walmsley@sifive.com: fixed checkpatch issue; minor commit
    message fix]
    Signed-off-by: Paul Walmsley

    Christoph Hellwig
     

16 Nov, 2019

1 commit

13 Nov, 2019

1 commit

  • 8083c629d   RISC-V: Add multiple compression image format. ... Browse Code »

    Currently, there is only support for .gz compression type
    for generating kernel Image.

    Add support for other compression methods(lzma, lz4, lzo, bzip2)
    that helps in generating a even smaller kernel image. Image.gz
    will still be the default compressed image.

    Signed-off-by: Atish Patra
    Signed-off-by: Paul Walmsley

    Atish Patra
     

15 Oct, 2019

1 commit

  • 2993c9b04   riscv: dts: HiFive Unleashed: add default chosen/stdout-path ... Browse Code »

    Add a default "stdout-path" to the kernel DTS file, as is present in many
    of the board DTS files elsewhere in the kernel tree. With this line
    present, earlyconsole can be enabled by simply passing "earlycon" on the
    kernel command line. No specific device details are necessary, since the
    kernel will use the stdout-path as the default.

    Signed-off-by: Paul Walmsley
    Reviewed-by: Atish Patra

    Paul Walmsley
     

20 Sep, 2019

2 commits

19 Sep, 2019

1 commit

  • b45e0c30b   riscv: dts: Add DT support for SiFive FU540 PWM driver ... Browse Code »

    Add the PWM DT node in SiFive FU540 soc-specific DT file.
    Enable the PWM nodes in HiFive Unleashed board-specific DT file.

    Signed-off-by: Yash Shah
    Cc: Palmer Dabbelt
    [paul.walmsley@sifive.com: added chip-specific compatible string;
    dropped reg-names string from pwm1]
    Signed-off-by: Paul Walmsley

    Yash Shah
     

01 Aug, 2019

1 commit

  • 11ae2d892   riscv: dts: fu540-c000: drop "timebase-frequency" ... Browse Code »

    On FU540-based systems, the "timebase-frequency" (RTCCLK) is sourced
    from an external crystal located on the PCB. Thus the
    timebase-frequency DT property should be defined by the board that
    uses the SoC, not the SoC itself. Drop the superfluous
    timebase-frequency property from the SoC DT data. (It's already
    present in the board DT data.)

    Signed-off-by: Paul Walmsley
    Reviewed-by: Bin Meng

    Paul Walmsley
     

23 Jul, 2019

1 commit

02 Jul, 2019

1 commit

27 Jun, 2019

1 commit

  • 45b03df28   riscv: dts: Re-organize the DT nodes ... Browse Code »

    As per the convention for any SOC device with external connection,
    define only device DT node in SOC DTSi file with status = "disabled"
    and enable device in Board DTS file with status = "okay"

    Reported-by: Anup Patel
    Signed-off-by: Yash Shah
    Signed-off-by: Paul Walmsley

    Yash Shah
     

17 Jun, 2019

3 commits

  • c35f1b87f   riscv: dts: add initial board data for the SiFive HiFive Unleashed ... Browse Code »

    Add initial board data for the SiFive HiFive Unleashed A00.

    Currently the data populated in this DT file describes the board
    DRAM configuration and the external clock sources that supply the
    PRCI.

    Signed-off-by: Paul Walmsley
    Signed-off-by: Paul Walmsley
    Tested-by: Loys Ollivier
    Tested-by: Kevin Hilman
    Cc: Rob Herring
    Cc: Mark Rutland
    Cc: Palmer Dabbelt
    Cc: Albert Ou
    Cc: Antony Pavlov
    Cc: devicetree@vger.kernel.org
    Cc: linux-riscv@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org

    Paul Walmsley
     
  • 72296bde4   riscv: dts: add initial support for the SiFive FU540-C000 SoC ... Browse Code »

    Add initial support for the SiFive FU540-C000 SoC. This is a 28nm SoC
    based around the SiFive U54-MC core complex and a TileLink
    interconnect.

    This file is expected to grow as more device drivers are added to the
    kernel.

    This patch includes a fix to the QSPI memory map due to a
    documentation bug, found by ShihPo Hung , adds
    entries for the I2C controller, and merges all DT changes that
    formerly were made dynamically by the riscv-pk BBL proxy kernel.

    Signed-off-by: Paul Walmsley
    Signed-off-by: Paul Walmsley
    Tested-by: Loys Ollivier
    Tested-by: Kevin Hilman
    Cc: Rob Herring
    Cc: Mark Rutland
    Cc: Palmer Dabbelt
    Cc: Albert Ou
    Cc: ShihPo Hung
    Cc: devicetree@vger.kernel.org
    Cc: linux-riscv@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org

    Paul Walmsley
     
  • 8d4e048d6   arch: riscv: add support for building DTB files from DT source data ... Browse Code »

    Similar to ARM64, add support for building DTB files from DT source
    data for RISC-V boards.

    This patch starts with the infrastructure needed for SiFive boards.
    Boards from other vendors would add support here in a similar form.

    Signed-off-by: Paul Walmsley
    Signed-off-by: Paul Walmsley
    Tested-by: Loys Ollivier
    Tested-by: Kevin Hilman
    Cc: Palmer Dabbelt
    Cc: Albert Ou

    Paul Walmsley
     

20 Nov, 2018

1 commit

  • c0fbcd991   RISC-V: Build flat and compressed kernel images ... Browse Code »

    This patch extends Linux RISC-V build system to build and install:
    Image - Flat uncompressed kernel image
    Image.gz - Flat and GZip compressed kernel image

    Quiet a few bootloaders (such as Uboot, UEFI, etc) are capable of
    booting flat and compressed kernel images. In case of Uboot, booting
    Image or Image.gz is achieved using bootm command.

    The flat and uncompressed kernel image (i.e. Image) is very useful
    in pre-silicon developent and testing because we can create back-door
    HEX files for RAM on FPGAs from Image.

    Signed-off-by: Anup Patel
    Signed-off-by: Palmer Dabbelt

    Anup Patel