30 Dec, 2020
2 commits
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[ Upstream commit 01324f9e88b5cfc1f4c26eef66bdcb52596c9af8 ]
The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
bypass.Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Reported-by: Claudiu Beznea
Signed-off-by: Alexandre Belloni
Link: https://lore.kernel.org/r/20201202125816.168618-1-alexandre.belloni@bootlin.com
Reviewed-by: Claudiu Beznea
Tested-by: Claudiu Beznea
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin -
[ Upstream commit 91274497c79170aaadc491d4ffe4de35495a060d ]
pmc_data_allocate() has been changed. pmc_data_free() was removed.
Adapt the code taking this into consideration. With this the programmable
clocks were also saved in sama7g5_pmc so that they could be later
referenced.Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Claudiu Beznea
Reviewed-by: Tudor Ambarus
Tested-by: Tudor Ambarus
Link: https://lore.kernel.org/r/1605800597-16720-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
21 Oct, 2020
1 commit
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…'clk-prima2' and 'clk-bcm' into clk-next
- Support qcom SM8150/SM8250 video and display clks
- Change how qcom's display port clks work* clk-ingenic:
clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate
clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT
clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
clk: ingenic: Use readl_poll_timeout instead of custom loop
clk: ingenic: Use to_clk_info() macro for all clocks* clk-at91:
clk: at91: sam9x60: support only two programmable clocks
clk: at91: clk-sam9x60-pll: remove unused variable
clk: at91: clk-main: update key before writing AT91_CKGR_MOR
clk: at91: remove the checking of parent_name* clk-kconfig:
clk: Restrict CLK_HSDK to ARC_SOC_HSDK* clk-imx:
clk: imx8mq: Fix usdhc parents order
clk: imx: imx21: Remove clock driver
clk: imx: gate2: Fix a few typos
clk: imx: Fix and update kerneldoc
clk: imx: fix i.MX7D peripheral clk mux flags
clk: imx: fix composite peripheral flags
clk: imx: Correct the memrepair clock on imx8mp
clk: imx: Correct the root clk of media ldb on imx8mp
clk: imx: vf610: Add CRC clock
clk: imx: Explicitly include bits.h
clk: imx8qxp: Support building i.MX8QXP clock driver as module
clk: imx8m: Support module build
clk: imx: Add clock configuration for ARMv7 platforms
clk: imx: Support building i.MX common clock driver as module
clk: composite: Export clk_hw_register_composite()
clk: imx6sl: Use BIT(x) to avoid shifting signed 32-bit value by 31 bits* clk-qcom:
clk: qcom: gdsc: Keep RETAIN_FF bit set if gdsc is already on
clk: qcom: Add display clock controller driver for SM8150 and SM8250
dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
clk: qcom: add video clock controller driver for SM8250
clk: qcom: add video clock controller driver for SM8150
dt-bindings: clock: add SM8250 QCOM video clock bindings
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
clk: qcom: gcc-msm8994: Add missing clocks, resets and GDSCs
clk/qcom: fix spelling typo
clk: qcom: gcc-sdm660: Fix wrong parent_map
clk: qcom: dispcc: Update DP clk ops for phy design
clk: qcom: gcc-msm8939: remove defined but not used variables
clk: qcom: ipq8074: make pcie0_rchng_clk_src static* clk-prima2:
clk: clk-prima2: fix return value check in prima2_clk_init()* clk-bcm:
clk: bcm2835: add missing release if devm_clk_hw_register fails
clk: bcm: rpi: Add register to control pixel bvb clk
15 Oct, 2020
1 commit
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According to datasheet (Chapter 29.16.13, PMC Programmable Clock Register)
there are only two programmable clocks on SAM9X60.Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1602686072-28296-1-git-send-email-claudiu.beznea@microchip.com
Acked-by: Nicolas Ferre
Signed-off-by: Stephen Boyd
14 Oct, 2020
3 commits
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Fix variable set but not used compilation warning.
Fixes: 43b1bb4a9b3e ("clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputs")
Reported-by: kernel test robot
Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1598338751-20607-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
SAMA5D2 datasheet specifies on chapter 33.22.8 (PMC Clock Generator
Main Oscillator Register) that writing any value other than
0x37 on KEY field aborts the write operation. Use the key when
selecting main clock parent.Fixes: 27cb1c2083373 ("clk: at91: rework main clk implementation")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1598338751-20607-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
There is no need to check parent_name variable while assigning it to
init.parent_names. parent_name variable is already checked at
the beginning of at91_clk_register_peripheral() function.Fixes: 6114067e437eb ("clk: at91: add PMC peripheral clocks")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1598338751-20607-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd
23 Sep, 2020
1 commit
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The at91sam9g45_pcr_layout is not used so drop it to fix build warning:
drivers/clk/at91/at91sam9g45.c:49:36: warning:
'at91sam9g45_pcr_layout' defined but not used [-Wunused-const-variable=]Signed-off-by: Krzysztof Kozlowski
Acked-by: Alexandre Belloni
Link: https://lore.kernel.org/r/20200916161740.14173-1-krzk@kernel.org
Signed-off-by: Stephen Boyd
24 Jul, 2020
18 commits
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Add clock support for SAMA7G5.
Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-19-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Add UTMI support for SAMA7G5. SAMA7G5's UTMI control is done via
XTALF register. Values written at bits 2..0 in this register
correspond to the on board crystal oscillator frequency.Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-18-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Some of the SAMA7G5 PLLs support multiple outputs (e.g. AUDIO PLL).
For these, split the PLL clock in two: fractional clock and
divider clock. In case PLLs supports multiple outputs (since these
outputs are dividers (with different settings) sharing the same
fractional part), it will register one fractional clock and multiple
divider clocks (dividers sharing the fractional clock).Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-17-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Add mux table option. This is necessary for IP versions that has
gaps in the range of available clock sources (e.g. SAMA7G5).Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-15-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Some peripheral clocks on SAMA7G5 supports requesting parent to change
its rate (image related clocks: csi, csi2dc, isc). Add support
so that if registered with this option the clock rate to be
requested from parent.Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-14-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Add master clock support (MCK1..4) for SAMA7G5. SAMA7G5's PMC has
multiple master clocks feeding different subsystems. One of them
feeds image subsystem and is changeable based on image subsystem
needs.Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-13-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Add mux table option. This is necessary for IP versions that has
gaps in the range of available clock sources (e.g. SAMA7G5).Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Pass the ID of changeable parent at registration. This will allow
the scalability of this clock driver with regards to the changeable
parent ID for versions of this IP where changeable parent is not the
last one in the parents list (e.g. SAMA7G5). With this the clock flags
are set to zero in case we have no changeable parent. Also in
clk_generated_best_diff() the *best_diff variable is check against
tmp_diff variable using ">=" operator instead of ">" so that in case
the requested frequency could be obtained using fix parents + gck
dividers but the clock also supports changeable parent to be able
to force the usage of the changeable parent.Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-11-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Replace conditional operator with double logical not as code
may be simpler to read.Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Chapter 57.7.5 of SAM9X60 datasheet specifies that the maximum drift of
this oscillator is +- 3KHz. Use that value and the formula at [1]
or the calculator at [2] to compute the PPB value.[1] https://www.everythingrf.com/rf-calculators/ppm-to-hz-calculator
[2] https://www.changpuak.ch/electronics/ppm_to_Hz_converter.phpFixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60")
Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-9-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Main RC oscillator frequency is 12MHz according to datasheet
(chapter 27.2).Fixes: 01e2113de9a52 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1595403506-8209-8-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
According to datasheet the range of 600-1200MHz is for the
frequency generated by the fractional part of the PLL (namely
Fcorepllck according to datasheet). With this in mind the output
range of the PLL itself (fractional + div), taking into account
that the divider is 8 bits wide, is 600/256-1200Hz=2.3-1200MHz.Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea
Link: https://lore.kernel.org/r/1595403506-8209-6-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Use logical or for range check. In case bestrate is not in
characteristics->output[0].min..characteristics->output[0].max
range we should return -ERANGE.Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1595403506-8209-5-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
According to datasheet mul mask is on bits 31..24.
Fixes: a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1595403506-8209-4-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
Check best_rate against available clock ranges.
Fixes: df70aeef6083 ("clk: at91: add generated clock driver")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1595403506-8209-3-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
__clk_determine_rate() may return error. Skip the current step
in case of error.Fixes: 1a1a36d72e3d3 ("clk: at91: clk-generated: make gclk determine audio_pll rate")
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1595403506-8209-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
syscon_node_to_regmap() will make the created regmap get and enable the
first clock it can parse from the device tree. This clock is not needed to
access the registers and should not be enabled at that time.Use device_node_to_regmap to resolve this as it looks up the regmap in
the same list but doesn't care about the clocks. This issue is detected
by lockdep when booting the sama5d3 with a device tree containing the
new clk bindings.This fix already happened in 6956eb33abb5 ("clk: at91: fix possible
deadlock") for the drivers that had been migrated to the new clk binding
back then. This does the same for the new drivers as well.Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Ahmad Fatoum
Link: https://lore.kernel.org/r/20200703073236.23923-1-a.fatoum@pengutronix.de
Acked-by: Alexandre Belloni
Signed-off-by: Stephen Boyd
27 May, 2020
6 commits
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We need to have clocks accessible via phandle to select them
as peripheral clock parent using assigned-clock-parents in DT.
Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available.Signed-off-by: Michał Mirosław
Acked-by: Alexandre Belloni
Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.pl
Signed-off-by: Stephen Boyd -
This exposes PROGx clocks for use in assigned-clocks DeviceTree property
for selecting PCKx parent clock.Signed-off-by: Michał Mirosław
Link: https://lkml.kernel.org/r/0054532c00163ddf405dad658b32f0d7d97fcc8e.1588630999.git.mirq-linux@rere.qmqm.pl
Acked-by: Alexandre Belloni
Signed-off-by: Stephen Boyd -
Alloc whole data structure in one block. This makes the code shorter,
more efficient and easier to extend in following patch.Signed-off-by: Michał Mirosław
Link: https://lkml.kernel.org/r/fc6f6d67b8cee0beace4a9d9cca7431e5efa769d.1588630999.git.mirq-linux@rere.qmqm.pl
Acked-by: Alexandre Belloni
Signed-off-by: Stephen Boyd -
of_find_matching_node() increment node's refcount. Call
of_node_put() to decrement it after it was used.Signed-off-by: Claudiu Beznea
Link: https://lkml.kernel.org/r/1588508289-10140-2-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
pmc_register_ops() is called for all AT91 devices. Return
-ENODEV in case of_find_matching_node() returns NULL.Signed-off-by: Claudiu Beznea
Link: https://lkml.kernel.org/r/1588508289-10140-1-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd -
PMC generates the peripheral clock for the PTC.
Signed-off-by: Codrin Ciubotariu
Link: https://lkml.kernel.org/r/20200515142720.290206-1-codrin.ciubotariu@microchip.com
Signed-off-by: Stephen Boyd
06 Apr, 2020
1 commit
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Pull clk updates from Stephen Boyd:
"There's not much to see in the core framework this time around.
Instead the majority of the diff is the normal collection of driver
additions for new SoCs and non-critical clk data fixes and updates.
The framework must be middle aged.The two biggest directories in the diffstat show that the Qualcomm and
Unisoc support added a handful of big drivers for new SoCs but that's
not really the whole story because those new drivers tend to add large
numbers of lines of clk data. There's a handful of AT91 clk drivers
added this time around too and a bunch of improvements to drivers like
the i.MX driver. All around lots of updates and fixes in various clk
drivers which is good to see.The core framework has only one real major change which has been
baking in next for the past couple months. It fixes the framework so
that it stops caching a clk's phase when the phase clk_op returns an
error. Before this change we would consider some negative errno as a
phase and that just doesn't make sense.Core:
- Don't show clk phase when it is invalidNew Drivers:
- Add support for Unisoc SC9863A clks
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and
at91sam9g45 SoCsUpdates:
- GPU GX GDSC support on Qualcomm sc7180
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update i.MX pll14xx driver to include new frequency entries for
pll1443x table, and return error for invalid PLL type
- Add missing of_node_put() call for a number of i.MX clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need
to change ARM PLL frequency. Thus, we can support core running
above 1GHz safely
- Update i.MX pfdv2 driver to check zero rate and use determine_rate
for getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for
imx7d
- Remove PMC clks from Tegra clk driver
- Improved clock/reset handling for the Renesas R-Car USB2 Clock
Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
- Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and
M3-N
- Update Amlogic audio clock gate hierarchy for meson8 and gxbb
- Update Amlogic g12a spicc clock sources
- Support for Ingenic X1000 TCU clks"* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits)
clk: sprd: fix to get a correct ibias of pll
dt-bindings: imx8mm-clock: Fix the file path
dt-bindings: imx8mq-clock: Fix the file path
clk: qcom: rpmh: Drop unnecessary semicolons
clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()
clk: tegra: Use NULL for pointer initialization
clk: sprd: add clocks support for SC9863A
clk: sprd: support to get regmap from parent node
clk: sprd: Add macros for referencing parents without strings
clk: sprd: Add dt-bindings include file for SC9863A
dt-bindings: clk: sprd: add bindings for sc9863a clock controller
dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific
clk: sprd: add gate for pll clocks
MAINTAINERS: dt: update reference for arm-integrator.txt
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
clk: mmp2: Add clock for fifth SD HCI on MMP3
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
clk: mmp2: Add clocks for the thermal sensors
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
clk: mmp2: add the GPU clocks
...
21 Mar, 2020
1 commit
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Add a driver for the PMC clocks of the at91rm9200.
Signed-off-by: Alexandre Belloni
Link: https://lkml.kernel.org/r/20200214145934.53648-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd
19 Feb, 2020
1 commit
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Move SAM9X60's PLL register offsets to PMC header so that the
definitions would also be available from arch/arm/mach-at91/pm_suspend.S.
This is necessary to disable/enable PLLA for SAM9X60 on suspend/resume.Signed-off-by: Claudiu Beznea
Acked-by: Stephen Boyd
Signed-off-by: Alexandre Belloni
Link: https://lore.kernel.org/r/1579522208-19523-7-git-send-email-claudiu.beznea@microchip.com
13 Feb, 2020
5 commits
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Add a driver for the PMC clocks of the at91sam9n12 family.
Signed-off-by: Alexandre Belloni
Link: https://lkml.kernel.org/r/20200116172316.426703-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd -
Add a driver for the PMC clocks of the sama5d3.
Signed-off-by: Alexandre Belloni
Link: https://lkml.kernel.org/r/20200110223033.1261791-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd -
Add a driver for the PMC clocks of the at91sam9g45 family.
Signed-off-by: Alexandre Belloni
Link: https://lkml.kernel.org/r/20200117210529.17490-1-alexandre.belloni@bootlin.com
Signed-off-by: Stephen Boyd -
SAM9X60 USB clock may have up to 3 parents. Save the number of parents in
driver's data structure and validate against it when setting parent.Signed-off-by: Claudiu Beznea
Link: https://lkml.kernel.org/r/1579261009-4573-5-git-send-email-claudiu.beznea@microchip.com
Acked-by: Alexandre Belloni
Signed-off-by: Stephen Boyd -
Use usbs_mask passed as argument. The usbs_mask is different for
SAM9X60.Fixes: 2423eeaead6f8 ("clk: at91: usb: Add sam9x60 support")
Signed-off-by: Claudiu Beznea
Link: https://lkml.kernel.org/r/1579261009-4573-4-git-send-email-claudiu.beznea@microchip.com
Acked-by: Alexandre Belloni
Signed-off-by: Stephen Boyd