Eric Lee / smarc-fsl-linux-kernel

21 Oct, 2020

1 commit

  • 3ab9a54f7   Merge branches 'clk-simplify', 'clk-ti', 'clk-tegra', 'clk-rockchip' and 'clk-me… ... Browse Code »

    …diatek' into clk-next

    - Small non-critical fixes for TI clk driver
    - Support Mediatek MT8167 clks

    * clk-simplify:
    clk: mediatek: fix platform_no_drv_owner.cocci warnings
    clk: mediatek: mt7629: simplify the return expression of mtk_infrasys_init
    clk: mediatek: mt6797: simplify the return expression of mtk_infrasys_init

    * clk-ti:
    clk: ti: dra7: add missing clkctrl register for SHA2 instance
    clk: ti: clockdomain: fix static checker warning
    clk: ti: autoidle: add checks against NULL pointer reference
    clk: keystone: sci-clk: add 10% slack to set_rate
    clk: keystone: sci-clk: cache results of last query rate operation
    clk: keystone: sci-clk: fix parsing assigned-clock data during probe

    * clk-tegra:
    clk: tegra: Drop !provider check in tegra210_clk_emc_set_rate()

    * clk-rockchip:
    clk: rockchip: Initialize hw to error to avoid undefined behavior
    clk: rockchip: rk3399: Support module build
    clk: rockchip: fix the clk config to support module build
    clk: rockchip: Export some clock common APIs for module drivers
    clk: rockchip: Export rockchip_register_softrst()
    clk: rockchip: Export rockchip_clk_register_ddrclk()
    clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls
    clk: rockchip: rk3308: drop unused mux_timer_src_p

    * clk-mediatek:
    clk: mediatek: Add MT8167 clock support
    dt-bindings: clock: mediatek: add bindings for MT8167 clocks
    clk: mediatek: add UART0 clock support

    Stephen Boyd
     

14 Oct, 2020

1 commit

  • a68224832   clk: mediatek: Add MT8167 clock support ... Browse Code »

    Add the following clock support for MT8167 SoC: topckgen, apmixedsys,
    infracfg, audsys, imgsys, mfgcfg, vdecsys.

    Signed-off-by: Fabien Parent
    Link: https://lore.kernel.org/r/20200918132303.2831815-2-fparent@baylibre.com
    Signed-off-by: Stephen Boyd

    Fabien Parent
     

09 Oct, 2020

1 commit

23 Sep, 2020

3 commits

14 Jun, 2020

1 commit

  • a7f7f6248   treewide: replace '---help---' in Kconfig files with 'help' ... Browse Code »

    Since commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over
    '---help---'"), the number of '---help---' has been gradually
    decreasing, but there are still more than 2400 instances.

    This commit finishes the conversion. While I touched the lines,
    I also fixed the indentation.

    There are a variety of indentation styles found.

    a) 4 spaces + '---help---'
    b) 7 spaces + '---help---'
    c) 8 spaces + '---help---'
    d) 1 space + 1 tab + '---help---'
    e) 1 tab + '---help---' (correct indentation)
    f) 1 tab + 1 space + '---help---'
    g) 1 tab + 2 spaces + '---help---'

    In order to convert all of them to 1 tab + 'help', I ran the
    following commend:

    $ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/'

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     

11 Jun, 2020

1 commit

  • 6f630784c   Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Browse Code »

    Pull clk updates from Stephen Boyd:
    "This time around we have four lines of diff in the core framework,
    removing a function that isn't used anymore. Otherwise the main new
    thing for the common clk framework is that it is selectable in the
    Kconfig language now. Hopefully this will let clk drivers and clk
    consumers be testable on more than the architectures that support the
    clk framework. The goal is to introduce some Kunit tests for the
    framework.

    Outside of the core framework we have the usual set of various driver
    updates and non-critical fixes. The dirstat shows that the new
    Baikal-T1 driver is the largest addition this time around in terms of
    lines of code. After that the x86 (Intel), Qualcomm, and Mediatek
    drivers introduce many lines to support new or upcoming SoCs. After
    that the dirstat shows the usual suspects working on their SoC support
    by fixing minor bugs, correcting data and converting some of their DT
    bindings to YAML.

    Core:
    - Allow the COMMON_CLK config to be selectable

    New Drivers:
    - Clk driver for Baikal-T1 SoCs
    - Mediatek MT6765 clock support
    - Support for Intel Agilex clks
    - Add support for X1830 and X1000 Ingenic SoC clk controllers
    - Add support for the new Renesas RZ/G1H (R8A7742) SoC
    - Add support for Qualcomm's MSM8939 Generic Clock Controller

    Updates:
    - Support IDT VersaClock 5P49V5925
    - Bunch of updates for HSDK clock generation unit (CGU) driver
    - Start making audio and GPU clks work on Marvell MMP2/MMP3 SoCs
    - Add some GPU, NPU, and UFS clks to Qualcomm SM8150 driver
    - Enable supply regulators for GPU gdscs on Qualcomm SoCs
    - Add support for Si5342, Si5344 and Si5345 chips
    - Support custom flags in Xilinx zynq firmware
    - Various small fixes to the Xilinx clk driver
    - A single minor rounding fix for the legacy Allwinner clock support
    - A few patches from Abel Vesa as preparation of adding audiomix
    clock support on i.MX
    - A couple of cleanups from Anson Huang for i.MX clk-sscg-pll and
    clk-pllv3 drivers
    - Drop dependency on ARM64 for i.MX8M clock driver, to support
    aarch32 mode on aarch64 hardware
    - A series from Peng Fan to improve i.MX8M clock drivers, using
    composite clock for core and bus clk slice
    - Set a better parent clock for flexcan on i.MX6UL to support CiA102
    defined bit rates
    - A couple changes for EMC frequency scaling on Tegra210
    - Support for CPU frequency scaling on Tegra20/Tegra30
    - New clk gate for CSI test pattern generator on Tegra210
    - Regression fixes for Samsung exynos542x and exynos5433 SoCs
    - Use of fallthrough; attribute for Samsung s3c24xx
    - Updates and fixup HDMI and video clocks on Meson8b
    - Fixup reset polarity on Meson8b
    - Fix GPU glitch free mux switch on Meson gx and g12
    - A minor fix for the currently unused suspend/resume handling on
    Renesas RZ/A1 and RZ/A2
    - Two more conversions of Renesas DT bindings to json-schema
    - Add support for the USB 2.0 clock selector on Renesas R-Car M3-W+"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (155 commits)
    clk: mediatek: Remove ifr{0,1}_cfg_regs structures
    clk: baikal-t1: remove redundant assignment to variable 'divider'
    clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible"
    dt-bindings: clock: Add a missing include to MMP Audio Clock binding
    dt: Add bindings for IDT VersaClock 5P49V5925
    clk: vc5: Add support for IDT VersaClock 5P49V6965
    clk: Add Baikal-T1 CCU Dividers driver
    clk: Add Baikal-T1 CCU PLLs driver
    dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
    dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
    clk: mediatek: assign the initial value to clk_init_data of mtk_mux
    clk: mediatek: Add MT6765 clock support
    clk: mediatek: add mt6765 clock IDs
    dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
    dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT6765 SoC
    dt-bindings: clock: mediatek: document clk bindings for Mediatek MT6765 SoC
    CLK: HSDK: CGU: add support for 148.5MHz clock
    CLK: HSDK: CGU: support PLL bypassing
    CLK: HSDK: CGU: check if PLL is bypassed first
    clk: clk-si5341: Add support for the Si5345 series
    ...

    Linus Torvalds
     

10 Jun, 2020

1 commit

  • 9ac1eafa8   clk: mediatek: Remove ifr{0,1}_cfg_regs structures ... Browse Code »

    These aren't used and the macros that reference them aren't used either.
    Remove the dead code to avoid compile warnings.

    Cc: Owen Chen
    Cc: Mars Cheng
    Cc: Macpaul Lin
    Fixes: 1aca9939bf72 ("clk: mediatek: Add MT6765 clock support")
    Reported-by: kbuild test robot
    Signed-off-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20200609211847.27366-1-sboyd@kernel.org

    Stephen Boyd
     

29 May, 2020

2 commits

  • 571cfadcc   clk: mediatek: assign the initial value to clk_init_data of mtk_mux ... Browse Code »

    When some new clock supports are introduced, e.g. [1]
    it might lead to an error although it should be NULL because
    clk_init_data is on the stack and it might have random values
    if using without initialization.
    Add the missing initial value to clk_init_data.

    [1] https://android-review.googlesource.com/c/kernel/common/+/1278046

    Fixes: a3ae549917f1 ("clk: mediatek: Add new clkmux register API")
    Signed-off-by: Weiyi Lu
    Reviewed-by: Matthias Brugger
    Cc:
    Link: https://lore.kernel.org/r/1590560749-29136-1-git-send-email-weiyi.lu@mediatek.com
    Signed-off-by: Stephen Boyd

    Weiyi Lu
     
  • 1aca9939b   clk: mediatek: Add MT6765 clock support ... Browse Code »

    Add MT6765 clock support, include topckgen, apmixedsys,
    infracfg, mcucfg and subsystem clocks.

    Signed-off-by: Owen Chen
    Signed-off-by: Mars Cheng
    Signed-off-by: Macpaul Lin
    Link: https://lore.kernel.org/r/1582278742-1626-6-git-send-email-macpaul.lin@mediatek.com
    Signed-off-by: Stephen Boyd

    Owen Chen
     

20 May, 2020

5 commits

  • 32956dda9   clk/soc: mediatek: mt6779: Bind clock driver from platform device ... Browse Code »

    The mmsys driver is now the top level entry point for the multimedia
    system (mmsys), we bind the clock driver by creating a platform device.
    We also bind the MediaTek DRM driver which is not yet implement and
    therefor will errror out for now.

    Signed-off-by: Matthias Brugger
    Reviewed-by: Chun-Kuang Hu
    Acked-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20200518113156.25009-3-matthias.bgg@kernel.org
    Signed-off-by: Matthias Brugger

    Matthias Brugger
     
  • cad4e3790   clk/soc: mediatek: mt6797: Bind clock driver from platform device ... Browse Code »

    The mmsys driver is now the top level entry point for the multimedia
    system (mmsys), we bind the clock driver by creating a platform device.
    We also bind the MediaTek DRM driver which is not yet implement and
    therefor will errror out for now.

    Signed-off-by: Matthias Brugger
    Reviewed-by: Chun-Kuang Hu
    Acked-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20200518113156.25009-2-matthias.bgg@kernel.org
    Signed-off-by: Matthias Brugger

    Matthias Brugger
     
  • 1f9adbc72   clk/soc: mediatek: mt8183: Bind clock driver from platform device ... Browse Code »

    The mmsys driver is now the top level entry point for the multimedia
    system (mmsys), we bind the clock driver by creating a platform device.
    We also bind the MediaTek DRM driver which is not yet implement and
    therefor will errror out for now.

    Signed-off-by: Matthias Brugger
    Reviewed-by: Chun-Kuang Hu
    Acked-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20200518113156.25009-1-matthias.bgg@kernel.org
    Signed-off-by: Matthias Brugger

    Matthias Brugger
     
  • c292b133b   clk / soc: mediatek: Bind clock and gpu driver for mt2701 ... Browse Code »

    Now that the mmsys driver is the top-level entry point for the
    multimedia subsystem, we could bind the clock and the gpu driver on
    those devices that is expected to work, so the drm driver is
    intantiated by the mmsys driver and display, hopefully, working again.

    Signed-off-by: Enric Balletbo i Serra
    Reviewed-by: Chun-Kuang Hu
    Acked-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20200401201736.2980433-3-enric.balletbo@collabora.com
    Signed-off-by: Matthias Brugger

    Enric Balletbo i Serra
     
  • 9c5a0a3a8   clk / soc: mediatek: Bind clock and gpu driver for mt2712 ... Browse Code »

    Now that the mmsys driver is the top-level entry point for the
    multimedia subsystem, we could bind the clock and the gpu driver on
    those devices that is expected to work, so the drm driver is
    intantiated by the mmsys driver and display, hopefully, working again on
    those devices.

    Signed-off-by: Enric Balletbo i Serra
    Reviewed-by: Chun-Kuang Hu
    Acked-by: Stephen Boyd
    Link: https://lore.kernel.org/r/20200401201736.2980433-2-enric.balletbo@collabora.com
    Signed-off-by: Matthias Brugger

    Enric Balletbo i Serra
     

13 Apr, 2020

1 commit

  • 13032709e   clk / soc: mediatek: Move mt8173 MMSYS to platform driver ... Browse Code »

    There is no strong reason for this to use CLK_OF_DECLARE instead of
    being a platform driver. Plus, MMSYS provides clocks but also a shared
    register space for the mediatek-drm and the mediatek-mdp
    driver. So move the MMSYS clocks to a new platform driver and also
    create a new MMSYS platform driver in drivers/soc/mediatek that
    instantiates the clock driver.

    Signed-off-by: Matthias Brugger
    Signed-off-by: Enric Balletbo i Serra
    Reviewed-by: CK Hu
    Reviewed-by: Stephen Boyd
    Signed-off-by: Matthias Brugger

    Matthias Brugger
     

05 Jan, 2020

1 commit

  • 333d2d19d   clk: Fix Kconfig indentation ... Browse Code »

    Adjust indentation from spaces to tab (+optional two spaces) as in
    coding style with command like:
    $ sed -e 's/^ /\t/' -i */Kconfig

    Signed-off-by: Krzysztof Kozlowski
    Link: https://lkml.kernel.org/r/1574306335-29026-1-git-send-email-krzk@kernel.org
    [sboyd@kernel.org: Fixup mediatek to have two spaces for help indent]
    Signed-off-by: Stephen Boyd

    Krzysztof Kozlowski
     

17 Oct, 2019

6 commits

21 Sep, 2019

1 commit

  • a703d279c   Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Browse Code »

    Pull clk updates from Stephen Boyd:
    "We have a small collection of core framework updates this time, mostly
    around clk registration by clk providers and debugfs "nice to haves"
    for rate constraints. I'll highlight that we're now setting the
    clk_init_data pointer inside struct clk_hw to NULL during
    clk_register(), which may break some drivers that thought they could
    use that pointer during normal operations. That change has been
    sitting in next for a while now but maybe something is still broken.
    We'l see. Other than that the core framework changes aren't invasive
    and they're fixing bugs, simplifying, and making things better.

    On the clk driver side we got the usual addition of new SoC support,
    new features for existing drivers, and bug fixes scattered throughout.
    The biggest diffstat is the Amlogic driver that gained CPU clk support
    in addition to migrating to the new way of specifying clk parents.
    After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
    support for various new SoCs and clock controllers from those vendors.

    Core:
    - Drop NULL checks in clk debugfs
    - Add min/max rates to clk debugfs
    - Set clk_init_data pointer inside clk_hw to NULL after registration
    - Make clk_bulk_get_all() return an 'id' corresponding to clock-names
    - Evict parents from parent cache when they're unregistered

    New Drivers:
    - Add clock driver for i.MX8MN SoCs
    - Support aspeed AST2600 SoCs
    - Support for Mediatek MT6779 SoCs
    - Support qcom SM8150 GCC and RPMh clks
    - Support qcom QCS404 WCSS clks
    - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
    - Addition of clock driver for Rockchip rk3308 SoCs

    Updates:
    - Add regulator support to the cdce925 clk driver
    - Add support for Raspberry Pi 4 bcm2711 SoCs
    - Add SDIO gate support to aspeed driver
    - Add missing of_node_put() calls in various clk drivers
    - Migrate Amlogic driver to new clock parent description method
    - Add DVFS support to Amlogic Meson g12
    - Add Amlogic Meson g12a reset support to the axg audio clock controller
    - Add sm1 support to the Amlogic Meson g12a clock controller
    - Switch i.MX8MM clock driver to platform driver
    - Add Hifi4 DSP related clocks for i.MX8QXP SoC
    - Fix Audio PLL setting and parent clock for USB
    - Misc i.MX8 clock driver improvements and corrections
    - Set floor ops for Qualcomm SD clks so that rounding works
    - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
    - Enable the Allwinner V3 SoC and fix the i2s clock for H6"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
    clk: Drop !clk checks in debugfs dumping
    clk: imx: imx8mn: fix pll mux bit
    clk: imx: imx8mm: fix pll mux bit
    clk: imx: clk-pll14xx: unbypass PLL by default
    clk: imx: pll14xx: avoid glitch when set rate
    clk: mvebu: ap80x: add AP807 clock support
    clk: mvebu: ap806: Prepare the introduction of AP807 clock support
    clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
    clk: mvebu: ap806: be more explicit on what SaR is
    clk: mvebu: ap80x-cpu: add AP807 CPU clock support
    clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
    dt-bindings: ap806: Document AP807 clock compatible
    dt-bindings: ap80x: Document AP807 CPU clock compatible
    clk: sprd: add missing kfree
    clk: at91: allow 24 Mhz clock as input for PLL
    clk: Make clk_bulk_get_all() return a valid "id"
    clk: actions: Fix factor clk struct member access
    clk: qcom: rcg: Return failure for RCG update
    clk: remove extra ---help--- tags in Kconfig
    clk: add include guard to clk-conf.h
    ...

    Linus Torvalds
     

18 Sep, 2019

3 commits

10 Sep, 2019

1 commit

  • 710774e04   clk: mediatek: Add MT6779 clock support ... Browse Code »

    Add MT6779 clock support, include topckgen, apmixedsys,
    infracfg, and subsystem clocks.

    Signed-off-by: mtk01761
    Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
    Signed-off-by: Stephen Boyd

    mtk01761
     

08 Aug, 2019

1 commit

23 Jul, 2019

1 commit

18 Jul, 2019

1 commit

  • 916f562fb   Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux ... Browse Code »

    Pull clk updates from Stephen Boyd:
    "This round of clk driver and framework updates is heavy on the driver
    update side. The two main highlights in the core framework are the
    addition of an bulk clk_get API that handles optional clks and an
    extra debugfs file that tells the developer about the current parent
    of a clk.

    The driver updates are dominated by i.MX in the diffstat, but that is
    mostly because that SoC has started converting to the clk_hw style of
    clk registration. The next big update is in the Amlogic meson clk
    driver that gained some support for audio, cpu, and temperature clks
    while fixing some PLL issues. Finally, the biggest thing that stands
    out is the conversion of a large part of the Allwinner sunxi-ng driver
    to the new clk parent scheme that uses less strings and more pointer
    comparisons to match clk parents and children up.

    In general, it looks like we have a lot of little fixes and tweaks
    here and there to clk data along with the normal addition of a handful
    of new drivers and a couple new core framework features.

    Core:
    - Add a 'clk_parent' file in clk debugfs
    - Add a clk_bulk_get_optional() API (with devm too)

    New Drivers:
    - Support gated clk controller on MIPS based BCM63XX SoCs
    - Support SiLabs Si5341 and Si5340 chips
    - Support for CPU clks on Raspberry Pi devices
    - Audsys clock driver for MediaTek MT8516 SoCs

    Updates:
    - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
    - Small frequency support for SiLabs Si544 chips
    - Slow clk support for AT91 SAM9X60 SoCs
    - Remove dead code in various clk drivers (-Wunused)
    - Support for Marvell 98DX1135 SoCs
    - Get duty cycle of generic pwm clks
    - Improvement in mmc phase calculation and cleanup of some rate defintions
    - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
    - Add GPIO, SNVS and GIC clocks for i.MX8 drivers
    - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
    - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
    - Add clks for new Exynos5422 Dynamic Memory Controller driver
    - Clock definition for Exynos4412 Mali
    - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
    - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
    - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
    - TI clock probing done from DT by default instead of firmware
    - Fix Amlogic Meson mpll fractional part and spread sprectrum issues
    - Add Amlogic meson8 audio clocks
    - Add Amlogic g12a temperature sensors clocks
    - Add Amlogic g12a and g12b cpu clocks
    - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
    - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
    - Add Clock Domain support on Renesas RZ/N1"

    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
    clk: consoldiate the __clk_get_hw() declarations
    clk: sprd: Add check for return value of sprd_clk_regmap_init()
    clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
    clk: Add Si5341/Si5340 driver
    dt-bindings: clock: Add silabs,si5341
    clk: clk-si544: Implement small frequency change support
    clk: add BCM63XX gated clock controller driver
    devicetree: document the BCM63XX gated clock bindings
    clk: at91: sckc: use dedicated functions to unregister clock
    clk: at91: sckc: improve error path for sama5d4 sck registration
    clk: at91: sckc: remove unnecessary line
    clk: at91: sckc: improve error path for sam9x5 sck register
    clk: at91: sckc: add support to free slow clock osclillator
    clk: at91: sckc: add support to free slow rc oscillator
    clk: at91: sckc: add support to free slow oscillator
    clk: rockchip: export HDMIPHY clock on rk3228
    clk: rockchip: add watchdog pclk on rk3328
    clk: rockchip: add clock id for hdmi_phy special clock on rk3228
    clk: rockchip: add clock id for watchdog pclk on rk3328
    clk: at91: sckc: add support for SAM9X60
    ...

    Linus Torvalds
     

13 Jul, 2019

1 commit

  • a993be372   Merge branches 'clk-debugfs', 'clk-unused', 'clk-refactor' and 'clk-qoriq' into clk-next ... Browse Code »

    - Add a 'clk_parent' file in clk debugfs
    - Remove dead code in various clk drivers

    * clk-debugfs:
    clk: Add clk_parent entry in debugfs

    * clk-unused:
    clk: qcom: Fix -Wunused-const-variable
    clk: mmp: frac: Remove set but not used variable 'prev_rate'
    clk: ti: Remove unused functions
    clk: mediatek: mt8516: Remove unused variable

    * clk-refactor:
    clk: clk-cdce706: simplify getting the adapter of a client
    clk: Simplify clk_core_can_round()

    * clk-qoriq:
    clk: qoriq: add support for lx2160a

    Stephen Boyd
     

08 Jun, 2019

1 commit

  • 60e9c3703   clk: mediatek: mt8516: Remove unused variable ... Browse Code »

    Variable 'ddrphycfg_parents' is defined static and initialized, but not
    used in the file.

    ../drivers/clk/mediatek/clk-mt8516.c:234:27: warning: ‘ddrphycfg_parents’ defined but not used [-Wunused-const-variable=]
    static const char * const ddrphycfg_parents[] __initconst = {
    ^~~~~~~~~~~~~~~~~

    Signed-off-by: Philippe Mazenauer
    Signed-off-by: Stephen Boyd

    Philippe Mazenauer
     

07 Jun, 2019

2 commits

31 May, 2019

1 commit

  • 1802d0bee   treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174 ... Browse Code »

    Based on 1 normalized pattern(s):

    this program is free software you can redistribute it and or modify
    it under the terms of the gnu general public license version 2 as
    published by the free software foundation this program is
    distributed in the hope that it will be useful but without any
    warranty without even the implied warranty of merchantability or
    fitness for a particular purpose see the gnu general public license
    for more details

    extracted by the scancode license scanner the SPDX license identifier

    GPL-2.0-only

    has been chosen to replace the boilerplate/reference in 655 file(s).

    Signed-off-by: Thomas Gleixner
    Reviewed-by: Allison Randal
    Reviewed-by: Kate Stewart
    Reviewed-by: Richard Fontana
    Cc: linux-spdx@vger.kernel.org
    Link: https://lkml.kernel.org/r/20190527070034.575739538@linutronix.de
    Signed-off-by: Greg Kroah-Hartman

    Thomas Gleixner
     

21 May, 2019

1 commit

08 May, 2019

1 commit

  • 2ed3b9103   Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and 'clk-imx' into clk-next ... Browse Code »

    - Qualcomm QCS404 CDSP clk support
    - Qualcomm QCS404 Turing clk support
    - Mediatek MT8183 clock support
    - Mediatek MT8516 clock support
    - Milbeaut M10V clk controller support

    * clk-renesas:
    clk: renesas: rcar-gen3: Remove unused variable
    clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value
    clk: renesas: r8a77980: Fix RPC-IF module clock's parent
    clk: renesas: rcar-gen3: Rename DRIF clocks
    clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC
    clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
    clk: renesas: rcar-gen3: Correct parent clock of HS-USB
    clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI
    clk: renesas: r8a774c0: Add Z2 clock
    clk: renesas: r8a77990: Add Z2 clock
    clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents
    math64: New DIV64_U64_ROUND_CLOSEST helper
    clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2
    clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset
    clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor
    clk: renesas: r9a06g032: Add missing PCI USB clock
    clk: renesas: r7s9210: Always use readl()
    clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register()

    * clk-qcom:
    clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998
    clk: qcom: Add QCS404 TuringCC
    clk: qcom: branch: Add AON clock ops
    dt-bindings: clock: Introduce Qualcomm Turing Clock controller
    clk: qcom: gcc-qcs404: Add CDSP related clocks and resets

    * clk-mtk:
    clk: mediatek: add clock driver for MT8516
    dt-bindings: mediatek: apmixedsys: add support for MT8516
    dt-bindings: mediatek: infracfg: add support for MT8516
    dt-bindings: mediatek: topckgen: add support for MT8516
    clk: mediatek: Allow changing PLL rate when it is off
    clk: mediatek: Add MT8183 clock support
    clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data
    clk: mediatek: Add dt-bindings for MT8183 clocks
    dt-bindings: ARM: Mediatek: Document bindings for MT8183
    clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data
    clk: mediatek: Add new clkmux register API
    clk: mediatek: Disable tuner_en before change PLL rate

    * clk-milbeaut:
    clock: milbeaut: Add Milbeaut M10V clock controller
    dt-bindings: clock: milbeaut: add Milbeaut clock description

    * clk-imx:
    clk: imx: correct pfdv2 gate_bit/vld_bit operations
    clk: imx: clk-pllv3: mark expected switch fall-throughs
    clk: imx8mq: Add dsi_ipg_div
    clk: imx: pllv4: add fractional-N pll support
    clk: imx: keep uart clock on during system boot
    clk: imx: correct i.MX7D AV PLL num/denom offset
    clk: imx6sll: Fix mispelling uart4_serial as serail
    clk: imx: pll14xx: drop unused variable
    clk: imx: rename clk-imx51-imx53.c to clk-imx5.c
    clk: imx5: Fix i.MX50 ESDHC clock registers
    clk: imx5: Fix i.MX50 mainbus clock registers
    clk: imx: Remove unused imx_get_clk_hw_fixed
    dt-bindings: clock: imx7ulp: remove SNVS clock
    clk: imx7ulp: remove snvs clock

    Stephen Boyd
     

26 Apr, 2019

1 commit