09 Jun, 2017
40 commits
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Remove usless 'fsl,wdog-reset' property in dts on v4.9
Signed-off-by: Robin Gong
(cherry picked from commit bfe33c0df6a7cba546fcc5b30609be277f499af2) -
align watchdog external reset output property with community
instead of "fsl,wdog_b".Signed-off-by: Robin Gong
(cherry picked from commit c07391d10d74a1c85a0978085a3ac0a761fb6410) -
ext_reset used instead of wdog_b on v4.9, no need wdog_b anymore.
Signed-off-by: Robin Gong
(cherry picked from commit b8009c3121f6ff5be170484dc7f0b600a0a720ec) -
CAAM uses DMA to transfer data to and from memory, if
DMA and CPU accessed data share the same cacheline cache
pollution will occur. Marking the result as cacheline aligned
moves it to a separate cache line.Signed-off-by: Radu Solea
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Remove whitespace.
Signed-off-by: Irina Tirdea
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Signed-off-by: Irina Tirdea
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In upstream, IMX7D_ARM_A7_ROOT_SRC uses imx_clk_mux2 for initialization,
while our code uses imx_clk_mux_flags_bus with additional flags
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE. In the end, both calls
set the flags of IMX7D_ARM_A7_ROOT_SRC clock to
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE.To align our code to upstream, we can safely use imx_clk_mux2.
Signed-off-by: Irina Tirdea
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Update imx7d clk platform code according to upstream commit
40e00ef ("clk: imx7d: add the missing ipg_root_clk").Signed-off-by: Irina Tirdea
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Default compile the usdhc driver into kernel
Signed-off-by: Haibo Chen
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Some i.MX SoCs don't define ARCH_MXC, so add COMPILE_TEST to let usdhc driver
also support for these i.MX SoCs.Signed-off-by: Haibo Chen
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Remove dependency of ARCH_MXC to support GPIO driver on
both ARMv7 and ARMv8 i.MX platforms.Signed-off-by: Anson Huang
Signed-off-by: Peng Fan -
Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, verify the cable state before reading the EDID. There is no point
in trying to read EDID (and print an error message), when there is no
device connected to HDMI connector.Signed-off-by: Robert Chiras
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Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, use the driver name, since there is more than one MIPI DSI driver.Signed-off-by: Robert Chiras
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Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, use the driver name, since there is more than one MIPI DSI driver.Signed-off-by: Robert Chiras
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Debug info should not be printed using pr_info on init. Use pr_debug
instead.
Also, use the driver name, since there is more than one MIPI DSI driver.Signed-off-by: Robert Chiras
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Debug info should not be printed using pr_info on init. Use pr_debug
instead.Signed-off-by: Robert Chiras
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Fix the same issue as commit bf23e0c5ea31 on imx6qp-saresd-hdcp board
Signed-off-by: Robin Gong
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When using fb_find_mode from fbdev/core with a specified user more,
it will return a screeninfo structure with the pixclock corresponding to
a different refresh rate than the requested one. For example, for
1920x1080@60 it will return pixclock=5780. When we get the videmode for
this screeninfo, it will have a refresh of 59Hz, instead of 60Hz.
If we use this mode as default mode when EDID cannot be read, on a
monitor with fixed refresh rate of 60Hz, it won't work. Therefore, we
should save the default mode, the nearest mode from CEA modes defined by
our own driver (which will have the correct refresh rate and pixclock for
the requested resolution).Signed-off-by: Robert Chiras
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Fix below pfuze probe issue by setting correct range of SW3B:
pfuze100-regulator 0-0008: pfuze200 found.
SW3B: Bringing 3300000uV into 1975000-1975000uV
SW3B: failed to apply 1975000-1975000uV constraint(-22)
pfuze100-regulator 0-0008: register regulatorSW3B failed
pfuze100-regulator: probe of 0-0008 failed with error -22
2020000.serial: ttymxc0 at MMIO 0x2020000 (irq = 19, base_baud = 5000000) is a IMXSigned-off-by: Anson Huang
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commit 70f2d20917bc ("MLK-14884 mmc: sdhci: make DDR50 tuning optionally")
want to make DDR50 card tuning optionally, but the code logic is not
right, the tuning of DDR50 card will also be impacted by the flag
'SDHCI_SDR50_NEEDS_TUNING'. e.g. imx6sl/imx6sx/imx6ul/imx7d default set
USE_TUNING_SDR50, which means on these SoC, DDR50 card still do tuning
even haven't the flag 'SDHCI_DDR50_NEEDS_TUNING'.This patch fix the logic issue, separate DDR50 and SDR50 card.
Signed-off-by: Haibo Chen
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Add USB OTG1 port ID pin for imx6ul-14x14-evk.dts
Acked-by: Peter Chen
Signed-off-by: Li Jun -
Add USB OTG1 port ID pin for imx6ull-14x14-evk.dts
Acked-by: Peter Chen
Signed-off-by: Li Jun -
restore pin setting for i2c in suspend/resume
Signed-off-by: Gao Pan
(cherry picked from commit 8aed73af218f25e0677b8980b3706246dd68790d)
Signed-off-by: Robin GongConflicts:
drivers/i2c/busses/i2c-imx.c -
Some SOC clock have some limits:
- ahb clock should be disabled before ipg.
- ahb and ipg clocks are required for MAC mii to work.
So, move the ahb clock to runtime pm together with ipg clock.Signed-off-by: Fugang Duan
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After commit 3e3274ab9ff3 ("mmc: sdhci-esdhc-imx: Use common
sdhci_suspend|resume_host()"), we lost the pins state store and save
in common sdhci_pltfm_{suspend|resume} API which results in the
pins state lost in state un-retainable suspend/resume, then
CMD transfer will meet timeout subsequently.Due to sdhci_pltfm_{suspend|resume} API becomes static after
that commit later, we then do manual pins state save and restore
in our platform suspend/resume API instead.Signed-off-by: Dong Aisheng
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Correct CD/WP pin in dts. Otherwise the card detection and write
protection function does not work.Signed-off-by: Dong Aisheng
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DDR50 tuning is optinally defined in sd 3.0 spec. Per IC guys
suggestion, it internally already uses a fixed optimized timing
and normally does not require tuning.Make it optionally and platform can claim SDHCI_DDR50_NEEDS_TUNING
support if it wants tuning.Signed-off-by: Dong Aisheng
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According to RM, Bit[11-8] is MUX_MODE which is configured by
the PIN_FUNC_ID automatically, specify it in config part is wrong
and violates the binding doc. So remove them all.It can also avoid the future confusing when customer wants to
configure a pad by following the exist code.Signed-off-by: Dong Aisheng
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Add i.MX7ULP binding doc. Note i.MX7ULP PIN_FUNC_ID consists of 4
integers as it shares one mux and config register as follows:Also fix the copyright.
Signed-off-by: Dong Aisheng
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'vin-supply' property used in ldo-bypass mode while 'vin-supply' deleted
in ldo-enable mode on v4.9 rather than dirctly switch 'supply' to internal
regulator and external pmic regulator on v4.1. Correct it for all *-ldo.dts,
otherwise, still work in ldo-bypass mode.Signed-off-by: Robin Gong
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I2C2 have to be disabled on hdcp board since those I2C2 bus pins
used for others, that said there is no all pmic regulators. In this
case, ldo-enable mode should be used and reg_arm/reg_soc/reg_pu should
be swithed to internal ldo instead. Otherwise, no reg_pu regulator
probed successfully by gpu driver, and cause gpu probe failed. Also,
cause cpufreq probe failed too.Signed-off-by: Robin Gong
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With current clock configuration we cannot derive bitclk for S20_3LE
format in SAI master mode. There was an attempt to fix this in commit
65e6b5f1b4a7 ("MLK-14536: ASoC: wm8960: Fix playback in CPU DAI master mode")
but this broke codec-master mode, thus the patch was partially reverted in
96f0d36e420 ("MLK-14798: arm: dts: imx6ul: Fix wm8960 codec master mode")So, remove S20_3LE support for SAI master mode. Clients using this
feature should use codec master mode, which is the default one in the
dts anyway.Signed-off-by: Daniel Baluta
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When 'CONFIG_MXC_PXP_CLIENT_DEVICE' disabled, the
'register_pxp_device' and 'unregister_pxp_device'
may cause multiple definitions compiling error.Signed-off-by: Fancy Fang
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For wm8962 we use imx-wm8962 machine driver which expects DAI CPU node
name to be "cpu-dai".Signed-off-by: Daniel Baluta
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The mem_base address is configured as the outbound
memory region twice when imx pcie ep/rc validation
is enabled.
Mask the one contained in desigware driver to fix
this issue.
Remove the usleep_range usage in designware driver,
since that function maybe used in imx noirq pm
calls.Signed-off-by: Richard Zhu
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pp->ops is not assigned properly, thus there
would be kernel panic when reboot ep board.
Initialized pp->ops in ep initializatione,
fix this issue.
don't call dw_pcie_wait_for_link because
the usleep is used in it.Signed-off-by: Richard Zhu
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There is error log "wm8962 3-001a: Unsupported BCLK ratio 6"
When the bitstream's format is S20_3LE.
The reason is that the pll output is samplerate*256, which
can't divide to clock samplerate*20*2. So in this patch change
the pll output to samplerate*384, and use the physical_width
for S20_3LE to calculate the bclk.Signed-off-by: Shengjiu Wang
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There is a bug in ssi sdma script cause dual fifo swap.Correct
it in sdma script.Signed-off-by: Robin Gong
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Commit 65e6b5f1b4a7 ("ASoC: wm8960: Fix playback in CPU DAI master
mode") broke wm8960 codec master mode by choosing "bad" SYSCLK values.This patch partially reverts commit mentioned above by restoring the
SYSCLK values. It turns out that using params_physical_width instead of
params_width in the previous patch it is enough to fix CPU DAI mode.Signed-off-by: Daniel Baluta
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This reverts commit c768ed336bba ("ASoC: fsl-sai: set xCR4/xCR5/xMR for
SAI master mode")This change was already introduced by commit 51659ca069ce ("ASoC: fsl-sai:
set xCR4/xCR5/xMR for SAI master mode") from upstream.Manually adjust the code to match the changes introduced by subsequent
commit b2936555bb38 ("MLK-13609: ASoC: fsl_sai: fix for synchronize mode")
by removing updates to FSL_SAI_TMR/FSL_SAI_RMR registers.Signed-off-by: Mihai Serban