Eric Lee / smarc-fsl-linux-kernel

27 Mar, 2015

2 commits

  • ee8e5d5fb   arm-cci: Split the code for PMU vs driver support ... Browse Code »

    This patch separates the PMU driver code from the low level
    CCI driver code and enables the PMU driver for ARM64.

    Introduces config options for both.

    ARM_CCI400_PORT_CTRL - controls the low level driver code for
    CCI400 ports.
    ARM_CCI400_PMU - controls the PMU driver code
    ARM_CCI400_COMMON - Common defintions for CCI400

    This patch also changes:
    ARM_CCI - common code for probing the CCI devices. This can be
    used for adding support for newer CCI versions(e.g, CCI-500).

    Cc: Bartlomiej Zolnierkiewicz
    Cc: Kukjin Kim
    Cc: Abhilash Kesavan
    Cc: Liviu Dudau
    Cc: Lorenzo Pieralisi
    Cc: Sudeep Holla
    Cc: Nicolas Pitre
    Cc: Punit Agrawal
    Acked-by: Sudeep Holla
    Acked-by: Nicolas Pitre
    Acked-by: Punit Agrawal
    Signed-off-by: Suzuki K. Poulose
    Signed-off-by: Will Deacon

    Suzuki K. Poulose
     
  • 772742a6c   arm-cci: Get rid of secure transactions for PMU driver ... Browse Code »

    Avoid secure transactions while probing the CCI PMU. The
    existing code makes use of the Peripheral ID2 (PID2) register
    to determine the revision of the CCI400, which requires a
    secure transaction. This puts a limitation on the usage of the
    driver on systems running non-secure Linux(e.g, ARM64).

    Updated the device-tree binding for cci pmu node to add the explicit
    revision number for the compatible field.

    The supported strings are :
    arm,cci-400-pmu,r0
    arm,cci-400-pmu,r1
    arm,cci-400-pmu - DEPRECATED. See NOTE below

    NOTE: If the revision is not mentioned, we need to probe the cci revision,
    which could be fatal on a platform running non-secure. We need a reliable way
    to know if we can poke the CCI registers at runtime on ARM32. We depend on
    'mcpm_is_available()' when it is available. mcpm_is_available() returns true
    only when there is a registered driver for mcpm. Otherwise, we assume that we
    don't have secure access, and skips probing the revision number(ARM64 case).

    The MCPM should figure out if it is safe to access the CCI. Unfortunately
    there isn't a reliable way to indicate the same via dtb. This patch doesn't
    address/change the current situation. It only deals with the CCI-PMU, leaving
    the assumptions about the secure access as it has been, prior to this patch.

    Cc: devicetree@vger.kernel.org
    Cc: Punit Agrawal
    Tested-by: Sudeep Holla
    Acked-by: Nicolas Pitre
    Acked-by: Mark Rutland
    Signed-off-by: Suzuki K. Poulose
    Signed-off-by: Will Deacon

    Suzuki K. Poulose
     

30 May, 2013

1 commit

  • ed69bdd8f   drivers: bus: add ARM CCI support ... Browse Code »

    On ARM multi-cluster systems coherency between cores running on
    different clusters is managed by the cache-coherent interconnect (CCI).
    It allows broadcasting of TLB invalidates and memory barriers and it
    guarantees cache coherency at system level through snooping of slave
    interfaces connected to it.

    This patch enables the basic infrastructure required in Linux to handle and
    programme the CCI component.

    Non-local variables used by the CCI management functions called by power
    down function calls after disabling the cache must be flushed out to main
    memory in advance, otherwise incoherency of those values may occur if they
    are sitting in the cache of some other CPU when power down functions
    execute. Driver code ensures that relevant data structures are flushed
    from inner and outer caches after the driver probe is completed.

    CCI slave port resources are linked to set of CPUs through bus masters
    phandle properties that link the interface resources to masters node in
    the device tree.

    Documentation describing the CCI DT bindings is provided with the patch.

    Signed-off-by: Lorenzo Pieralisi
    Signed-off-by: Nicolas Pitre

    Lorenzo Pieralisi