28 Oct, 2016
1 commit
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When changing from one data interface setting to another, one has to
ensure a specific sequence which is described in the ONFI spec.One of these constraints is that the CE line has go high after a reset
before a command can be sent with the new data interface setting, which
is not guaranteed by the current implementation.Rework the nand_reset() function and all the call sites to make sure the
CE line is asserted and released when required.Also make sure to actually apply the new data interface setting on the
first die.Signed-off-by: Boris Brezillon
Fixes: d8e725dd8311 ("mtd: nand: automate NAND timings selection")
Reviewed-by: Sascha Hauer
Tested-by: Marc Gonzalez
09 Oct, 2016
1 commit
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Introduction of the MTD pairing scheme concept.
23 Sep, 2016
9 commits
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Provide a nand_cleanup() function to free all nand related resources
without unregistering the mtd device.
This should allow drivers to call mtd_device_unregister() and handle
its return value and still being able to cleanup all nand related
resources.Signed-off-by: Richard Weinberger
Signed-off-by: Daniel Walter
Signed-off-by: Boris Brezillon -
The generic NAND DT bindings allows one to tweak the ECC strength and
step size to their need. It can be used to lower the ECC strength to
match a bootloader/firmware config, but might also be used to get a better
reliability.In the latter case, the user might want to use the maximum ECC strength
without having to explicitly calculate the exact value (this value not
only depends on the OOB size, but also on the NAND controller, and can
be tricky to extract).Add a generic 'nand-ecc-maximize' DT property and the associated
NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best
ECC strength and step-size on their own.Signed-off-by: Boris Brezillon
Acked-by: Rob Herring -
The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.Signed-off-by: Boris Brezillon
Signed-off-by: Sascha Hauer -
The nand layer will need ONFI mode 0 to use it as timing mode
before and right after reset.Signed-off-by: Sascha Hauer
Signed-off-by: Boris Brezillon -
onfi_init_data_interface() initializes a data interface with
values from a given ONFI mode.Signed-off-by: Sascha Hauer
Signed-off-by: Boris Brezillon -
Currently we have no data structure to fully describe a NAND timing.
We only have struct nand_sdr_timings for NAND timings in SDR mode,
but nothing for DDR mode and also no container to store both types
of timing.
This patch adds struct nand_data_interface which stores the timing
type and a union of different timings. This can be used to pass to
drivers in order to configure the timing.
Add kerneldoc for struct nand_sdr_timings while touching it anyway.Signed-off-by: Sascha Hauer
Signed-off-by: Boris Brezillon -
When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().Signed-off-by: Sascha Hauer
Signed-off-by: Boris Brezillon -
'extern' is not necessary for function declarations. To prevent
people from adding the keyword to new declarations remove the
existing ones.Signed-off-by: Sascha Hauer
Signed-off-by: Boris Brezillon -
The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.Signed-off-by: Marc Gonzalez
Signed-off-by: Boris Brezillon
15 Sep, 2016
1 commit
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MLC and TLC NAND devices are using NAND cells exposing more than one bit,
but instead of attaching all the bits in a given cell to a single NAND
page, each bit is usually attached to a different page. This concept is
called 'page pairing', and has significant impacts on the flash storage
usage.
The main problem showed by these devices is that interrupting a page
program operation may not only corrupt the page we are programming
but also the page it is paired with, hence the need to expose to MTD
users the pairing scheme information.The pairing APIs allows one to query pairing information attached to a
given page (here called wunit), or the other way around (the wunit
pointed by pairing information).
It also provides several helpers to help the conversion between absolute
offsets and wunits, and query the number of pairing groups.Signed-off-by: Boris Brezillon
Reviewed-by: Brian Norris
16 Jul, 2016
1 commit
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Pull NAND changes from Boris Brezillon:
"""
This pull request contains only one notable change:
* Addition of the MTK NAND controller driverAnd a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* A few fixes/improvements for the xway NAND controller driver
* A few fixes for the sunxi NAND controller driver
* Support for DMA in the sunxi NAND driver
* Support for the sunxi NAND controller IP embedded in A23/A33 SoCs
* Addition for bitflips detection in erased pages to the brcmnand driver
* Support for new brcmnand IPs
* Update of the OMAP-GPMC binding to support DMA channel description
"""
10 Jun, 2016
1 commit
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I got device with ESMT (Elite Semiconductor Memory Technology Inc)
F59L1G81MA flash that was detected as:
[ 0.852034] nand: device found, Manufacturer ID: 0xc8, Chip ID: 0xd1
[ 0.858402] nand: Unknown NAND 128MiB 3,3V 8-bit
[ 0.863031] nand: 128MiB, SLC, page size: 2048, OOB size: 64According to the F59L1G81MA datasheet (and Read Id documentation) C8h is
a "Maker Code" which should mean ESMT. Add it to fix above "Unknown".Signed-off-by: Rafał Miłecki
Signed-off-by: Boris Brezillon
02 Jun, 2016
2 commits
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Do not pass retlen to hardware driver read/write functions. Update it in
spi-nor generic driver instead.Signed-off-by: Michal Suchanek
Signed-off-by: Brian Norris
Tested-by Cyrille Pitchen
Acked-by: Michal Suchanek
Tested-by: Michal Suchanek -
Change the return value of spi-nor device read and write methods to
allow returning amount of data transferred and errors as
read(2)/write(2) does.Also, start handling positive returns in spi_nor_read(), since we want
to convert drivers to start returning the read-length both via *retlen
and the return code. (We don't need to do the same transition process
for spi_nor_write(), since ->write() didn't used to have a return code
at all.)Signed-off-by: Michal Suchanek
Signed-off-by: Brian Norris
Tested-by Cyrille Pitchen
Acked-by: Michal Suchanek
Tested-by: Michal Suchanek
11 May, 2016
1 commit
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Also note the GigaDevice JEDEC ID.
No write-protect support yet, since this flash uses a different status
register layout.Cc: Ezequiel Garcia
Signed-off-by: Brian Norris
Acked-by: Marek Vasut
06 May, 2016
7 commits
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Updates from Boris Brezillon:
This pull request contains the following infrastructure changes:
* introduction of the ECC algo concept to extend the ECC mode one
* replacement of the nand_ecclayout infrastructure by something more
future-proof.
* addition of an mtd-activity led trigger to replace the nand-activity
oneAnd a bunch of specific NAND driver improvements/fixes. Here are the
changes that are worth mentioning:
* rework of the OMAP GPMC and NAND drivers
* prepare the sunxi NAND driver to receive DMA support
* handle bitflips in erased pages on GPMI revisions that do not support
this in hardware.* tag 'nand/for-4.7' of github.com:linux-nand/linux: (152 commits)
mtd: brcmnand: respect ECC algorithm set by NAND subsystem
gpmi-nand: Handle ECC Errors in erased pages
Documentation: devicetree: deprecate "soft_bch" nand-ecc-mode value
mtd: nand: add support for "nand-ecc-algo" DT property
mtd: mtd: drop NAND_ECC_SOFT_BCH enum value
mtd: drop support for NAND_ECC_SOFT_BCH as "soft_bch" mapping
mtd: nand: read ECC algorithm from the new field
mtd: nand: fsmc: validate ECC setup by checking algorithm directly
mtd: nand: set ECC algorithm to Hamming on fallback
staging: mt29f_spinand: set ECC algorithm explicitly
CRIS v32: nand: set ECC algorithm explicitly
mtd: nand: atmel: set ECC algorithm explicitly
mtd: nand: davinci: set ECC algorithm explicitly
mtd: nand: bf5xx: set ECC algorithm explicitly
mtd: nand: omap2: Fix high memory dma prefetch transfer
mtd: nand: omap2: Start dma request before enabling prefetch
mtd: nandsim: add __init attribute
mtd: nand: move of_get_nand_xxx() helpers into nand_base.c
mtd: nand: sh_flctl: rely on generic DT parsing done in nand_scan_ident()
mtd: nand: mxc: rely on generic DT parsing done in nand_scan_ident()
... -
This value should not be part of nand_ecc_modes_t as it specifies
algorithm not a mode. We successfully managed to introduce new "algo"
field which is respected now.Signed-off-by: Rafał Miłecki
Signed-off-by: Boris Brezillon -
Now that all MTD drivers have moved to the mtd_ooblayout_ops model we can
safely remove the struct nand_ecclayout definition, and all the remaining
places where it was still used.Signed-off-by: Boris Brezillon
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Now that all NAND drivers have switched to mtd_ooblayout_ops, we can kill
the ecc->layout field.Signed-off-by: Boris Brezillon
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Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users. Modify the onenand drivers to switch to this
approach.Signed-off-by: Boris Brezillon
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Now that mtd_ooblayout_ecc() returns the ECC byte position using the
OOB free method, we can get rid of the fsmc_nand_eccplace struct.Signed-off-by: Boris Brezillon
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Implementing the mtd_ooblayout_ops interface is the new way of exposing
ECC/OOB layout to MTD users.Signed-off-by: Boris Brezillon
20 Apr, 2016
6 commits
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Replace the default nand_ecclayout definitions for large and small page
devices with the equivalent mtd_ooblayout_ops.Signed-off-by: Boris Brezillon
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ECC layout definitions are currently exposed using the nand_ecclayout
struct which embeds oobfree and eccpos arrays with predefined size.
This approach was acceptable when NAND chips were providing relatively
small OOB regions, but MLC and TLC now provide OOB regions of several
hundreds of bytes, which implies a non negligible overhead for everybody
even those who only need to support legacy NANDs.Create an mtd_ooblayout_ops interface providing the same functionality
(expose the ECC and oobfree layout) without the need for this huge
structure.The mtd->ecclayout is now deprecated and should be replaced by the
equivalent mtd_ooblayout_ops. In the meantime we provide a wrapper around
the ->ecclayout field to ease migration to this new model.Signed-off-by: Boris Brezillon
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Add an mtd_set_ecclayout() helper function to avoid direct accesses to the
mtd->ecclayout field. This will ease future reworks of ECC layout
definition.Signed-off-by: Boris Brezillon
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In order to make the ecclayout definition completely dynamic we need to
rework the way the OOB layout are defined and iterated.Create a few mtd_ooblayout_xxx() helpers to ease OOB bytes manipulation
and hide ecclayout internals to their users.Signed-off-by: Boris Brezillon
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Export the default read/write oob functions (for the standard and syndrome
scheme), so that drivers can use them for their raw implementation and
implement their own functions for the normal oob operation.This is required if your ECC engine is capable of fixing some of the OOB
data. In this case you have to overload the ->read_oob() and ->write_oob(),
but if you don't specify the ->read/write_oob_raw() functions they are
assigned to the ->read/write_oob() implementation, which is not what you
want.Signed-off-by: Boris Brezillon
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Our nand_ecc_modes_t is already a bit abused by value NAND_ECC_SOFT_BCH.
This enum should store ECC mode only and putting algorithm details there
is a bad idea. It would result in too many values impossible to support
in a sane way.To solve this problem let's add a new enum. We'll have to modify all
drivers to set it properly but once it's done it'll be possible to drop
NAND_ECC_SOFT_BCH. That will result in a cleaner design and more
possibilities like setting ECC algorithm for hardware ECC mode.Signed-off-by: Rafał Miłecki
Signed-off-by: Boris Brezillon
13 Apr, 2016
1 commit
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There's no reason for having mtd_write_oob inlined in mtd.h header.
Move it to mtdcore.c where it belongs.Signed-off-by: Ezequiel Garcia
Acked-by: Boris Brezillon
Signed-off-by: Jacek Anaszewski
04 Apr, 2016
1 commit
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When map_word gets too large, we use a lot of kernel stack, and for
MTD_MAP_BANK_WIDTH_32, this means we use more than the recommended
1024 bytes in a number of functions:drivers/mtd/chips/cfi_cmdset_0020.c: In function 'cfi_staa_write_buffers':
drivers/mtd/chips/cfi_cmdset_0020.c:651:1: warning: the frame size of 1336 bytes is larger than 1024 bytes [-Wframe-larger-than=]
drivers/mtd/chips/cfi_cmdset_0020.c: In function 'cfi_staa_erase_varsize':
drivers/mtd/chips/cfi_cmdset_0020.c:972:1: warning: the frame size of 1208 bytes is larger than 1024 bytes [-Wframe-larger-than=]
drivers/mtd/chips/cfi_cmdset_0001.c: In function 'do_write_buffer':
drivers/mtd/chips/cfi_cmdset_0001.c:1835:1: warning: the frame size of 1240 bytes is larger than 1024 bytes [-Wframe-larger-than=]This can be avoided if all operations on the map word are done
indirectly and the stack gets reused between the calls. We can
mostly achieve this by selecting MTD_COMPLEX_MAPPINGS whenever
MTD_MAP_BANK_WIDTH_32 is set, but for the case that no other
bank width is enabled, we also need to use a non-constant
map_bankwidth() to convince the compiler to use less stack.Signed-off-by: Arnd Bergmann
[Brian: this patch mostly achieves its goal by forcing
MTD_COMPLEX_MAPPINGS (and the accompanying indirection) for 256-bit
mappings; the rest of the change is mostly a wash, though it helps
reduce stack size slightly. If we really care about supporting
256-bit mappings though, we should consider rewriting some of this
code to avoid keeping and assigning so many 256-bit objects on the
stack.]
Signed-off-by: Brian Norris
11 Mar, 2016
1 commit
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One of the arguments passed to struct nand_chip's block_bad op is
'getchip', which, if true, is supposed to get and select the nand device,
and later unselect and release the device.This op is intended to be replaceable by drivers. The drivers shouldn't
be responsible for selecting/unselecting chip. Like other ops, the chip
should already be selected before the block_bad op is called.Remove the getchip argument from the block_bad op and
nand_block_checkbad. Move the chip selection to nand_block_isbad, since it
is the only caller to nand_block_checkbad which requires chip selection.Modify nand_block_bad (the default function for the op) such that it
doesn't select the chip.Remove the getchip argument from the bad_block funcs in cafe_nand,
diskonchip and docg4 drivers.Reviewed-by: Boris Brezillon
Signed-off-by: Archit Taneja
Signed-off-by: Brian Norris
08 Mar, 2016
4 commits
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Some flash support a bit in the status register that inverts protection
so that it applies to the bottom of the flash, not the top. This yields
additions to the protection range table, as noted in the comments.Because this feature is not universal to all flash that support
lock/unlock, control it via a new flag.Signed-off-by: Brian Norris
Tested-by: Ezequiel Garcia -
nand_bch_init() requires several arguments which could directly be deduced
from the mtd device. Get rid of those useless parameters.nand_bch_init() is also requiring the caller to provide a proper eccbytes
value, while this value could be deduced from the ecc.size and
ecc.strength value. Fallback to eccbytes calculation when it is set to 0.Signed-off-by: Boris Brezillon
Signed-off-by: Brian Norris -
Currently, all MTD drivers/sublayers exposing an OOB area are
doing the same kind of test to extract the available OOB size
based on the mtd_info and mtd_oob_ops structures.
Move this common logic into an inline function and make use of it.Signed-off-by: Boris Brezillon
Suggested-by: Priit Laes
Signed-off-by: Brian Norris -
ecclayout->oobavail is just redundant with the mtd->oobavail field.
Moreover, it prevents static const definition of ecc layouts since the
NAND framework is calculating this value based on the ecclayout->oobfree
field.Signed-off-by: Boris Brezillon
Signed-off-by: Brian Norris
13 Feb, 2016
1 commit
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As of commit 876fe76d793d03077eb61ba3afab4a383f46c554
"mtd: maps: physmap: Add reference counter to set_vpp()"
the comment in the header file is incorrect and misleading.
Fix it up.Cc: Russell King
Cc: Paul Parsons
Fixes: 876fe76d793d ("mtd: maps: physmap: Add reference counter to set_vpp()")
Signed-off-by: Linus Walleij
Signed-off-by: Brian Norris
27 Jan, 2016
2 commits
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This field is not set in any board file and can thus be dropped.
Signed-off-by: Boris Brezillon
Signed-off-by: Brian Norris -
Signed-off-by: Boris Brezillon
Signed-off-by: Brian Norris