11 May, 2016
1 commit
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Alex Barba discovered Broadcom NS2 GICv2m
implementation has an erratum where the MSI data needs to be the SPI
number subtracted by an offset of 32, for the correct MSI interrupt
to be triggered.Here we are adding the workaround based on readings from the MSI_IIDR
register, which contains a value unique to Broadcom NS2 GICv2mReported-by: Alex Barba
Acked-by: Marc Zyngier
Signed-off-by: Ray Jui
Signed-off-by: Marc Zyngier
19 Feb, 2016
1 commit
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Moving an SPI around doesn't require any extra work from the rest
of the stack, and specially not for MSI-generated SPIs.It is then worth returning IRQ_SET_MASK_OK_DONE instead of
IRQ_SET_MASK_OK, and simplify the other irqchips that rely on
this behaviour (GICv2m and Marvell's ODMI controller).Signed-off-by: Marc Zyngier
Acked-by: Thomas Petazzoni
Link: https://lkml.kernel.org/r/1455894029-17270-1-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper
29 Dec, 2015
2 commits
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This patch contain fixes for v2m resources and SPI ranges:
* Fix off-by-one error when set up v2m resource end range in
gicv2m_acpi_init().* Fix the off-by-one print error for SPI range.
* Use %pR to properly print resource range information.
Both ACPI and DT should now print:
GICv2m: range[mem 0xe1180000-0xe1180fff], SPI[64:319]
Suggested-by: Bjorn Helgaas
Signed-off-by: Suravee Suthikulpanit
Cc: Lorenzo Pieralisi
Cc: Will Deacon
Cc: Catalin Marinas
Cc:
Cc:
Cc:
Cc:
Cc:
Cc:
Cc:
Cc:
Link: http://lkml.kernel.org/r/1450830263-28914-1-git-send-email-Suravee.Suthikulpanit@amd.com
Signed-off-by: Thomas Gleixner -
…/maz/arm-platforms into irq/core
Pull another round of GIC changes from Marc:
ACPI support for GIV-v2m
21 Dec, 2015
2 commits
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This patch introduces gicv2m_acpi_init(), which uses information
in MADT GIC MSI frames structure to initialize GICv2m driver.
It also exposes gicv2m_init() function, which simplifies callers
to a single GICv2m init function.Reviewed-by: Marc Zyngier
Tested-by: Duc Dang
Acked-by: Rafael J. Wysocki
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Hanjun Guo
Signed-off-by: Marc Zyngier -
This patch replaces the struct device_node with struct fwnode_handle
since this structure is common between DT and ACPI.It also refactors gicv2m_init_one() to prepare for ACPI support.
The only functional change is removing the node name from pr_info.Reviewed-by: Marc Zyngier
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Marc Zyngier
16 Dec, 2015
1 commit
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On the error path, the v2m drivers drops the refcount on the parent
node instead of doing it on the node that generated the error.
Humph...Reported-by: Thomas Petazzoni
Signed-off-by: Marc Zyngier
15 Oct, 2015
1 commit
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The GICv2m driver is so far limited to a single MSI frame, but
nothing prevents an implementation from having several of them.This patch expands the driver to enumerate all frames, keeping
the first one as the canonical identifier for the MSI domains.Signed-off-by: Marc Zyngier
Tested-by: Duc Dang
Cc:
Cc: Suravee Suthikulpanit
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1444822037-16983-3-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
14 Oct, 2015
3 commits
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As we continue to push of_node towards the outskirts of irq domains,
let's start tackling the case of msi_create_irq_domain and its little
friends.This has limited impact in both PCI/MSI, platform MSI, and a few
drivers.Signed-off-by: Marc Zyngier
Tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-17-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
Since we now have a generic data structure to express an
interrupt specifier, convert all hierarchical irqchips that
are OF based to use a fwnode_handle as part of their alloc
and xlate (which becomes translate) callbacks.As most of these drivers have dependencies (they exchange IRQ
specifiers), change them all in a single, massive patch...Signed-off-by: Marc Zyngier
Reviewed-and-tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-6-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
The struct irq_domain contains a "struct device_node *" field
(of_node) that is almost the only link between the irqdomain
and the device tree infrastructure.In order to prepare for the removal of that field, convert all
users to use irq_domain_get_of_node() instead.Signed-off-by: Marc Zyngier
Reviewed-and-tested-by: Hanjun Guo
Tested-by: Lorenzo Pieralisi
Cc:
Cc: Tomasz Nowicki
Cc: Suravee Suthikulpanit
Cc: Graeme Gregory
Cc: Jake Oshins
Cc: Jiang Liu
Cc: Jason Cooper
Cc: Rafael J. Wysocki
Link: http://lkml.kernel.org/r/1444737105-31573-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
10 Oct, 2015
1 commit
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APM X-Gene GICv2m implementation has an erratum where the
MSI data needs to be the offset from the spi_start in order to
trigger the correct MSI interrupt. This is different from the
standard GICv2m implementation where the MSI data is the absolute
value within the range from spi_start to (spi_start + num_spis)
of each v2m frame.This patch reads MSI_IIDR register (present in all GICv2m
implementations) to identify X-Gene GICv2m implementation and
apply workaround to change the data portion of MSI vector.Reviewed-by: Marc Zyngier
Signed-off-by: Duc Dang
Signed-off-by: Marc Zyngier
15 Sep, 2015
1 commit
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After GICv2m was enabled for 32-bit ARM kernel, a warning popped up:
drivers/irqchip/irq-gic-v2m.c: In function gicv2m_compose_msi_msg:
drivers/irqchip/irq-gic-v2m.c:100:2: warning: right shift count >= width
of type [enabled by default]
msg->address_hi = (u32) (addr >> 32);
^This patch fixes it by using proper macros for splitting up the value.
Signed-off-by: Pavel Fedin
Reviewed-by: Marc Zyngier
Signed-off-by: Marc Zyngier
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stuart Yoder
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1442142873-20213-4-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
30 Jul, 2015
2 commits
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In order to support non-PCI MSI with GICv2m, add the minimal
required entry points for the MSI domain, which is actually almost
nothing (we just use the defaults provided by the core code).Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-18-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner -
GICv2m only uses the msi_controller structure as a way to match
the host bridge with its MSI HW, and thus the msi_domain.But now that we can directly associate an msi_domain with a device,
there is no use keeping this msi_controller around.Just remove all traces of msi_controller from the driver. Also
tag the inner (non-PCI) domain with DOMAIN_BUS_NEXUS.Signed-off-by: Marc Zyngier
Cc:
Cc: Yijing Wang
Cc: Ma Jun
Cc: Lorenzo Pieralisi
Cc: Duc Dang
Cc: Hanjun Guo
Cc: Bjorn Helgaas
Cc: Jiang Liu
Cc: Jason Cooper
Link: http://lkml.kernel.org/r/1438091186-10244-17-git-send-email-marc.zyngier@arm.com
Signed-off-by: Thomas Gleixner
26 Nov, 2014
1 commit
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ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new register frame. This allows a GICv2 based system to support
MSI with minimal changes.Signed-off-by: Suravee Suthikulpanit
[maz: converted the driver to use stacked irq domains,
updated changelog]
Signed-off-by: Marc Zyngier
Link: https://lkml.kernel.org/r/1416941243-7181-2-git-send-email-marc.zyngier@arm.com
Signed-off-by: Jason Cooper