20 Sep, 2011
1 commit
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dma_async_device_register will re-init chan_id and chancnt,
so whatever chan_id and chancnt are set in drivers, they will
be re-written by dma_async_device_register.Cc: Nicolas Ferre
Cc: Viresh Kumar
Cc: Vinod Koul
Cc: Piotr Ziecik
Cc: Yong Wang
Cc: Jaswinder Singh
Cc: Pelagicore AB
Signed-off-by: Barry Song
Acked-by: Viresh Kumar
Signed-off-by: Vinod Koul
29 May, 2011
1 commit
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* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (33 commits)
x86: poll waiting for I/OAT DMA channel status
maintainers: add dma engine tree details
dmaengine: add TODO items for future work on dma drivers
dmaengine: Add API documentation for slave dma usage
dmaengine/dw_dmac: Update maintainer-ship
dmaengine: move link order
dmaengine/dw_dmac: implement pause and resume in dwc_control
dmaengine/dw_dmac: Replace spin_lock* with irqsave variants and enable submission from callback
dmaengine/dw_dmac: Divide one sg to many desc, if sg len is greater than DWC_MAX_COUNT
dmaengine/dw_dmac: set residue as total len in dwc_tx_status if status is !DMA_SUCCESS
dmaengine/dw_dmac: don't call callback routine in case dmaengine_terminate_all() is called
dmaengine: at_hdmac: pause: no need to wait for FIFO empty
pch_dma: modify pci device table definition
pch_dma: Support new device ML7223 IOH
pch_dma: Support I2S for ML7213 IOH
pch_dma: Fix DMA setting issue
pch_dma: modify for checkpatch
pch_dma: fix dma direction issue for ML7213 IOH video-in
dmaengine: at_hdmac: use descriptor chaining help function
dmaengine: at_hdmac: implement pause and resume in atc_control
...Fix up trivial conflict in drivers/dma/dw_dmac.c
25 May, 2011
1 commit
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Nobody is currently maintaining dw_dmac. We are using dw_dmac for SPEAr13xx and
are currently maintaining it. After discussing with Vinod, sending this patch to
update maintainer-ship of dw_dmac.Signed-off-by: Viresh Kumar
Acked-by: Havard Skinnemoen
Signed-off-by: Vinod Koul
19 May, 2011
1 commit
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Haavard's e-mail address at Atmel is no longer valid.
Signed-off-by: Jean Delvare
Acked-by: Havard Skinnemoen
Signed-off-by: Jiri Kosina
13 May, 2011
5 commits
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Some peripherals like amba-pl011 needs pause to be implemented in DMA controller
drivers. This also returns correct status from dwc_tx_status() in case chan is
paused.Signed-off-by: Linus Walleij
Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
dmaengine routines can be called from interrupt context and with interrupts
disabled. Whereas spin_unlock_bh can't be called from such contexts. So this
patch converts all spin_*_bh routines to irqsave variants.Also, spin_lock() used in tasklet is converted to irqsave variants, as tasklet
can be interrupted, and dma requests from such interruptions may also call
spin_lock.Now, submission from callbacks are permitted as per dmaengine framework. So we
shouldn't hold any locks while calling callbacks. As locks were taken by parent
routines, so releasing them before calling callbacks doesn't look clean enough.
So, locks are taken inside all routine now, whereever they are required. And
dwc_descriptor_complete is always called without taking locks.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
If len passed in sg for slave_sg transfers is greater than DWC_MAX_COUNT, then
driver programmes controller incorrectly. This patch adds code to handle this
situation by allocation more than one desc for same sg.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
If transfer status is !=DMA_SUCCESS, return total transfer len as residue,
instead of zero.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
If dmaengine_terminate_all() is called for dma channel, then it doesn't make
much sense to call registered callback routine. While in case of success or
failure it must be called.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul
31 Mar, 2011
1 commit
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dwc_scan_descriptors scans all descriptors from active_list in case transfer is
not completed. It compares first_desc->lli.llp, and then all childrens of its
tx_list. But it doesn't compare its own address, i.e. first_desc->txd.phys, as
this is what we have initially programmed into the controller register. So this
causes dma to stop and finish a transfer, which was never started. And thus
fail.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul
07 Mar, 2011
10 commits
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This patch sets default Burst length for all transfer to 16. This will
enhance performance when user doesn't have any chan->private data.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
Msize or Burst Size is peripheral dependent in case of prep_slave_sg and
cyclic_prep transfers, and in case of memcpy transfers it is platform dependent.
So msize configuration must come from platform data.Also some peripherals (ex: JPEG), need to be flow controller for dma transfers,
so this information in case of slave_sg & cyclic_prep transfers must come from
platform data.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
In Synopsys designware, channel priority is programmable. This patch adds
support for passing channel priority through platform data. By default Ascending
channel priority will be followed, i.e. channel 0 will get highest priority and
channel 7 will get lowest.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
In SPEAr Platform channels 4-7 have more Fifo depth. So we must get better
channel first. This patch introduces concept of channel allocation order in
dw_dmac. If user doesn't pass anything or 0, than normal (ascending) channel
allocation will follow, else channels will be allocated in descending order.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
dwc_desc_get checks all descriptors for DMA_CTRL_ACK before allocating them for
transfers. And descriptors are not marked with DMA_CRTL_ACK after transfer
finishes. Thus descriptor once used is not usable again. This patch marks
descriptors with DMA_CRTL_ACK after dma xfer finishesSigned-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
Every descriptor can transfer a maximum count of 4095 (12 bits, in control reg),
So we must have DWC_MAX_COUNT as 4095 instead of 2048.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
Lock must be taken before calling dwc_scan_descriptors, as this may
access/modify shared data and queues. dwc_tx_status wasn't taking lock before
calling this routine. This patch add code that takes lock before calling
dwc_scan_descriptors.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
dwc_complete_all and other routines was removing all descriptors from dwc->queue
and pushing them to dwc->active_list. Only one was required to be removed. Also
we are calling dwc_dostart, once list is fixed.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul -
In some cases users of dw_dmac are initialized before dw_dmac, and if they try
to use dw_dmac, they simply fail. So its better we register init() routine
of driver using subsys_initcall() instead of module_init(), so that dma driver
is available at the earliest possible.Signed-off-by: Viresh Kumar
Signed-off-by: Vinod Koul
30 Jan, 2011
3 commits
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Some platforms (e.g. Picochip PC3XX) have multiple DMA controllers
where some may be used for slave transfers and others for general
purpose memcpy type transfers. Add a .is_private boolean to the
platform data structure so that controllers can be marked as private
so that the DMA_PRIVATE capability will be set for that controller.Signed-off-by: Jamie Iles
Signed-off-by: Dan Williams -
Some platforms have flexible mastering capabilities and this needs
to be selected at runtime. If the platform has specified private
data in the form of the dw_dma_slave then fetch the source and
destination masters from here. If this isn't present, default to
the previous of 0 and 1.v2: cleanup whitespace
Acked-by: Hans-Christian Egtvedt
Signed-off-by: Jamie Iles
Signed-off-by: Dan Williams -
Some hardware (picoChip picoXCell in particular) sometimes has
the block transfer complete bit being set for a channel after the
whole transfer has completed. If we don't have any transfers in the
active list then don't bother to scan the descriptors. This often
happens in normal operation and doesn't require the channel to be
reset.v2: cleanup whitespace
Signed-off-by: Jamie Iles
Signed-off-by: Dan Williams
18 May, 2010
1 commit
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This adds an argument to the DMAengine control function, so that
we can later provide control commands that need some external data
passed in through an argument akin to the ioctl() operation
prototype.[dan.j.williams@intel.com: fix up some missed conversions]
Signed-off-by: Linus Walleij
Signed-off-by: Dan Williams
27 Mar, 2010
3 commits
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Simple conditional struct filler to cut out some duplicated code.
Signed-off-by: Dan Williams
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Convert the device_is_tx_complete() operation on the
DMA engine to a generic device_tx_status()operation which
can return three states, DMA_TX_RUNNING, DMA_TX_COMPLETE,
DMA_TX_PAUSED.[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij
Acked-by: Mark Brown
Cc: Maciej Sosnowski
Cc: Nicolas Ferre
Cc: Pavel Machek
Cc: Li Yang
Cc: Guennadi Liakhovetski
Cc: Paul Mundt
Cc: Ralf Baechle
Cc: Haavard Skinnemoen
Cc: Magnus Damm
Cc: Liam Girdwood
Cc: Joe Perches
Cc: Roland Dreier
Signed-off-by: Dan Williams -
Convert the device_terminate_all() operation on the
DMA engine to a generic device_control() operation
which can now optionally support also pausing and
resuming DMA on a certain channel. Implemented for the
COH 901 318 DMAC as an example.[dan.j.williams@intel.com: update for timberdale]
Signed-off-by: Linus Walleij
Acked-by: Mark Brown
Cc: Maciej Sosnowski
Cc: Nicolas Ferre
Cc: Pavel Machek
Cc: Li Yang
Cc: Guennadi Liakhovetski
Cc: Paul Mundt
Cc: Ralf Baechle
Cc: Haavard Skinnemoen
Cc: Magnus Damm
Cc: Liam Girdwood
Cc: Joe Perches
Cc: Roland Dreier
Signed-off-by: Dan Williams
31 Dec, 2009
1 commit
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* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
drivers/dma: Correct use after free
drivers/dma: drop unnecesary memset
ioat2,3: put channel hardware in known state at init
async_tx: expand async raid6 test to cover ioatdma corner case
ioat3: fix p-disabled q-continuation
sh: fix DMA driver's descriptor chaining and cookie assignment
dma: at_hdmac: correct incompatible type for argument 1 of 'spin_lock_bh'
23 Dec, 2009
1 commit
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memset of 0 is not needed after kzalloc
The semantic patch that makes this change is as follows:
(http://coccinelle.lip6.fr/)//
@@
expression x;
statement S;
@@x = kzalloc(...);
if (x == NULL) S
... when != x
-memset(x,0,...);//Signed-off-by: Julia Lawall
Signed-off-by: Dan Williams
16 Dec, 2009
1 commit
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Signed-off-by: Alexey Dobriyan
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
23 Sep, 2009
1 commit
09 Sep, 2009
2 commits
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Dan Williams wrote:
... DMA-slave clients request specific channels and know the hardware
details at a low level, so it should not be too high an expectation to
push dma mapping responsibility to the client.Also this patch includes DMA_COMPL_{SRC,DEST}_UNMAP_SINGLE support for
dw_dmac driver.Acked-by: Maciej Sosnowski
Acked-by: Nicolas Ferre
Signed-off-by: Atsushi Nemoto
Signed-off-by: Dan Williams -
Drop dw_dmac's use of tx_list from struct dma_async_tx_descriptor in
preparation for removal of this field.Cc: Haavard Skinnemoen
Signed-off-by: Dan Williams
22 Jul, 2009
1 commit
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This patch reworks platform driver power management code
for dw_dmac from legacy late/early callbacks to dev_pm_ops.The callbacks are converted for CONFIG_SUSPEND like this:
suspend_late() -> suspend_noirq()
resume_early() -> resume_noirq()Signed-off-by: Magnus Damm
Acked-by: Greg Kroah-Hartman
Acked-by: Pavel Machek
Signed-off-by: Rafael J. Wysocki
04 Apr, 2009
1 commit
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* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx:
dma: Add SoF and EoF debugging to ipu_idmac.c, minor cleanup
dw_dmac: add cyclic API to DW DMA driver
dmaengine: Add privatecnt to revert DMA_PRIVATE property
dmatest: add dma interrupts and callbacks
dmatest: add xor test
dmaengine: allow dma support for async_tx to be toggled
async_tx: provide __async_inline for HAS_DMA=n archs
dmaengine: kill some unused headers
dmaengine: initialize tx_list in dma_async_tx_descriptor_init
dma: i.MX31 IPU DMA robustness improvements
dma: improve section assignment in i.MX31 IPU DMA driver
dma: ipu_idmac driver cosmetic clean-up
dmaengine: fail device registration if channel registration fails
02 Apr, 2009
1 commit
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This patch adds a cyclic DMA interface to the DW DMA driver. This is
very useful if you want to use the DMA controller in combination with a
sound device which uses cyclic buffers.Using a DMA channel for cyclic DMA will disable the possibility to use
it as a normal DMA engine until the user calls the cyclic free function
on the DMA channel. Also a cyclic DMA list can not be prepared if the
channel is already active.Signed-off-by: Hans-Christian Egtvedt
Acked-by: Haavard Skinnemoen
Acked-by: Maciej Sosnowski
Signed-off-by: Dan Williams
26 Mar, 2009
1 commit
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Centralize this common initialization (and one case where ipu_idmac is
duplicating ->chan initialization).Signed-off-by: Dan Williams
25 Mar, 2009
1 commit
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Cc: Dan Williams
Acked-by: Greg Kroah-Hartman
Signed-off-by: Kay Sievers
19 Feb, 2009
1 commit
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The conversion of atmel-mci to dma_request_channel missed the
initialization of the channel dma_slave information. The filter_fn passed
to dma_request_channel is responsible for initializing the channel's
private data. This implementation has the additional benefit of enabling
a generic client-channel data passing mechanism.Reviewed-by: Atsushi Nemoto
Signed-off-by: Dan Williams
Acked-by: Haavard Skinnemoen
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
07 Jan, 2009
1 commit
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Resolves:
WARNING: at drivers/base/core.c:122 device_release+0x4d/0x52()
Device 'dma0chan0' does not have a release() function, it is broken and must be fixed.The dma_chan_dev object is introduced to gear-match sysfs kobject and
dmaengine channel lifetimes. When a channel is removed access to the
sysfs entries return -ENODEV until the kobject can be released.The bulk of the change is updates to existing code to handle the extra
layer of indirection between a dma_chan and its struct device.Reported-by: Alexander Beregalov
Acked-by: Stephen Hemminger
Cc: Haavard Skinnemoen
Signed-off-by: Dan Williams