29 Oct, 2018
3 commits
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Fix: hexdump: /sys/bus/nvmem/devices/imx-ocotp0/nvmem: Input/output error
Address space [272,543] is invalid address space on 8QXP, reading from SCU
will get SC_ERR_PARAM. So ignore these words when reading fuse.BuildInfo:
- SCFW 8dcff26, IMX-MKIMAGE ea027c4b, ATF
- U-Boot 2017.03-imx_v2017.03_4.9.51_imx8_beta1+g6dc7b0fSigned-off-by: Peng Fan
-
Add i.MX8MQ support and Fix read.
When offset is not 4 bytes aligned, directly shift righty by 2 bits
will cause reading out wrong data. Since imx ocotp only supports
4 bytes reading once, we need handle offset is not 4 bytes aligned
and enlarge the bytes to 4 bytes aligned. After finished reading,
copy the needed data from buffer to caller and free buffer.Signed-off-by: Peng Fan
-
Add imx-scu-ocotp driver to support i.MX8QM/QXP.
The usage, add an entry in ocotp node, such as the test_1 entry:
ocotp: ocotp {
#address-cells = ;
#size-cells = ;
compatible = "fsl,imx8qm-ocotp", "syscon";test_1: test_1@40 {
reg = ;
bits = ;
};
};Then in your device node, add this:
node: node {
.....
nvmem-cells = ;
nvmem-cell-names = "test_1";
};Then in your driver, using the following piece code:
+#include
struct nvmem_cell *cell;
u8 *val;
size_t len;
int i;
cell = devm_nvmem_cell_get(&pdev->dev, "test_1");
if (IS_ERR(cell)) {
if (PTR_ERR(cell) == -EPROBE_DEFER)
return -EPROBE_DEFER;
}
val = nvmem_cell_read(cell, &len);The val points the contents that you need.
After shutdown or driver remove, use this:
devm_nvmem_cell_put(&pdev->dev, cell);Note: we not reuse the imx-ocotp driver, because mix scu api with
legacy code will cost many maintenance efforts. When we have common
api support, we could merge the two.Signed-off-by: Peng Fan
24 Aug, 2018
1 commit
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[ Upstream commit 87ed1405ef09d29a14df43295f7b6a93b63bfe6e ]
In commit ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on
Qcom chips") you can see a call like:devm_nvmem_cell_get(dev, NULL);
Note that the cell ID passed to the function is NULL. This is because
the qcom-qusb2 driver is expected to work only on systems where the
PHY node is hooked up via device-tree and is nameless.This works OK for the most part. The first thing nvmem_cell_get()
does is to call of_nvmem_cell_get() and there it's documented that a
NULL name is fine. The problem happens when the call to
of_nvmem_cell_get() returns -EINVAL. In such a case we'll fall back
to nvmem_cell_get_from_list() and eventually might (if nvmem_cells
isn't an empty list) crash with something that looks like:strcmp
nvmem_find_cell
__nvmem_device_get
nvmem_cell_get_from_list
nvmem_cell_get
devm_nvmem_cell_get
qusb2_phy_probeThere are several different ways we could fix this problem:
One could argue that perhaps the qcom-qusb2 driver should be changed
to use of_nvmem_cell_get() which is allowed to have a NULL name. In
that case, we'd need to add a patche to introduce
devm_of_nvmem_cell_get() since the qcom-qusb2 driver is using devm
managed resources.One could also argue that perhaps we could just add a name to
qcom-qusb2. That would be OK but I believe it effectively changes the
device tree bindings, so maybe it's a no-go.In this patch I have chosen to fix the problem by simply not crashing
when a NULL cell_id is passed to nvmem_cell_get().NOTE: that for the qcom-qusb2 driver the "nvmem-cells" property is
defined to be optional and thus it's expected to be a common case that
we would hit this crash and this is more than just a theoretical fix.Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Douglas Anderson
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
03 Aug, 2018
1 commit
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[ Upstream commit 50808bfcc14b854775a9f1d0abe3dac2babcf5c3 ]
Function nvmem_reg_read can return a non zero value indicating an error.
This returned value must be read and error propagated to
nvmem_cell_prepare_write_buffer. Silence the following gcc warning (W=1):drivers/nvmem/core.c:1093:9: warning: variable 'rc' set but
not used [-Wunused-but-set-variable]Signed-off-by: Mathieu Malaterre
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
18 Sep, 2017
2 commits
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of_get_next_parent() increments the refcount of the returned node.
It should be put when done.Signed-off-by: Masahiro Yamada
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
When writing data that exceeds the nvmem size to a nvmem sysfs file
using the sh redirection operator >, the shell hangs, trying to
write the out-of-range bytes endlessly.Fix the problem by returning EFBIG described in man 2 write.
Similar change was done for binary sysfs files on commit
0936896056365349afa867c16e9f9100a6707cbfSigned-off-by: Guy Shapiro
Cc: linux-api@vger.kernel.org
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
28 Aug, 2017
4 commits
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"p" is the list iterator so it can't be NULL. Static checkers complain
about this unnecessary check because we dereference the list iterator to
get the next item in the list so we'd be in trouble if it really was
NULL. I have removed the check.Signed-off-by: Dan Carpenter
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
This function does a quick and easy read of an u32 value without any
kind of resource management code on the consumer side.Signed-off-by: Leonard Crestez
Reviewed-by: Shawn Guo
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.Signed-off-by: Rob Herring
Cc: Srinivas Kandagatla
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Commit a53e35db70d1 ("reset: Ensure drivers are explicit when requesting
reset lines") started to transition the reset control request API calls
to explicitly state whether the driver needs exclusive or shared reset
control behavior. Convert all drivers requesting exclusive resets to the
explicit API call so the temporary transition helpers can be removed.No functional changes.
Cc: Srinivas Kandagatla
Cc: Joachim Eastwood
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Philipp Zabel
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
17 Jul, 2017
1 commit
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As the comments from Heiko Stuebner that compatible
should not contain any placeholders, this patch fix it for rk3228 SoC.Note that this is a fix for v4.13, due to fixing the current non-standard
binding name that should not become part of an official kernel release.Signed-off-by: Frank Wang
Acked-by: Rob Herring
Reviewed-by: Heiko Stuebner
Signed-off-by: Greg Kroah-Hartman
09 Jun, 2017
5 commits
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This adds the necessary data for handling eFuse on the rk322x.
Signed-off-by: Finley Xiao
Acked-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Adding entries to nvmem_cells and deleting entries from it is
protected by nvmem_cells_mutex. Therefore this mutex should
also protect iterating over the list.Signed-off-by: Heiner Kallweit
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Call put_device() in nvmem_unregister() to make sure nvmem_release
gets called freeing up allocated resources.Cc: cphealy@gmail.com
Cc: Srinivas Kandagatla
Cc: Maxime Ripard
Signed-off-by: Andrey Smirnov
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Make sure to deregister and release the nvmem device and underlying
memory on registration errors.Note that the private data must be freed using put_device() once the
struct device has been initialised.Also note that there's a related reference leak in the deregistration
function as reported by Mika Westerberg which is being fixed separately.Fixes: b6c217ab9be6 ("nvmem: Add backwards compatibility support for older EEPROM drivers.")
Fixes: eace75cfdcf7 ("nvmem: Add a simple NVMEM framework for nvmem providers")
Cc: stable # 4.3
Cc: Andrew Lunn
Cc: Srinivas Kandagatla
Cc: Mika Westerberg
Signed-off-by: Johan Hovold
Acked-by: Andrey Smirnov
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
- use data write offset to write otp data instead of read offset
- use OTP program command 0x8 to write otp with ECC rather than just
command 0xA without ECCFixes: 9d59c6e8ae27 ("nvmem: Add the Broadcom OTP controller driver")
Signed-off-by: Oza Pawandeep
Signed-off-by: Scott Branden
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
10 May, 2017
1 commit
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Pull ARM SoC driver updates from Olof Johansson:
"Driver updates for ARM SoCs:Reset subsystem, merged through arm-soc by tradition:
- Make bool drivers explicitly non-modular
- New support for i.MX7 and Arria10 reset controllersPATA driver for Palmchip BK371 (acked by Tejun)
Power domain drivers for i.MX (GPC, GPCv2)
- Moved out of mach-imx for GPC
- Bunch of tweaks, fixes, etcPMC support for Tegra186
SoC detection support for Renesas RZ/G1H and RZ/G1N
Move Tegra flow controller driver from mach directory to drivers/soc
- (Power management / CPU power driver)Misc smaller tweaks for other platforms"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits)
soc: pm-domain: Fix the mangled urls
soc: renesas: rcar-sysc: Add support for R-Car H3 ES2.0
soc: renesas: rcar-sysc: Add support for fixing up power area tables
soc: renesas: Register SoC device early
soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
soc: imx: gpc: add defines for domain index
soc: imx: Add GPCv2 power gating driver
dt-bindings: Add GPCv2 power gating driver
ARM/clk: move the ICST library to drivers/clk
ARM: plat-versatile: remove stale clock header
ARM: keystone: Drop PM domain support for k2g
soc: ti: Add ti_sci_pm_domains driver
dt-bindings: Add TI SCI PM Domains
PM / Domains: Do not check if simple providers have phandle cells
PM / Domains: Add generic data pointer to genpd data struct
soc/tegra: Add initial flowctrl support for Tegra132/210
soc/tegra: flowctrl: Add basic platform driver
soc/tegra: Move Tegra flowctrl driver
ARM: tegra: Remove unnecessary inclusion of flowctrl header
...
08 Apr, 2017
8 commits
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Implement write routine for OCOTP controller found in i.MX6 SoC's.
Furthermore add locking to the read function to prevent race conditions.
The write routine code is based on the fsl_otp driver from Freescale.Signed-off-by: Richard Leitner
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
When reading a "read locked" value from the OCOTP controller on i.MX6
SoC's an error bit is set. This bit has to be cleared by software before
any new write, read or reload access can be issued.Therefore clear it after we detect such an "locked read".
Signed-off-by: Richard Leitner
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Add i.MX7D support.
There is 16 banks, each bank 4 words.Signed-off-by: Peng Fan
Cc: Srinivas Kandagatla
Cc: Maxime Ripard
Cc: Shawn Guo
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
This adds a readonly nvmem driver for the i.MX IC Identification Module
(IIM). The IIM is found on the older i.MX SoCs like the i.MX25, i.MX27,
i.MX31, i.MX35, i.MX51 and the i.MX53.The IIM can control up to 8 fuse banks with 256 bit each. Not all of the
banks are equipped on the different SoCs. The actual number of fuses
differ from 512 on the i.MX27 and 1152 on the i.MX53.The fuses are one time writable, but writing is currently not supported
in the driver.Signed-off-by: Michael Grzeschik
Signed-off-by: Sascha Hauer
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Assign the correct dev pointer to struct ocotp_priv during probe. This
is needed to display dev_* messages correctly. Furthermore harmonize
the usage of dev (instead of &pdev->dev) in the probe function.Signed-off-by: Richard Leitner
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
The H3 SoC have a bigger SID controller, which has its direct read
address at 0x200 position in the SID block, not 0x0.Also, H3 SID controller has some silicon bug that makes the direct read
value wrong at cold boot, add code to workaround the bug. (This bug has
already been fixed on A64 and later SoCs)Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Sometimes the SID device have more memory address space than the real
NVMEM size (for the registers used to read/write the SID).Fetch the NVMEM size from device compatible, rather than the memory
address space's length, in order to prepare for adding some
registers-based read support.Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Currently the nvmem core expect the config to provide a name and ID
that are then used to create the device name. When no device name is
given 'nvmem' is used. However if there is several such anonymous
devices they all get named 'nvmem0', which doesn't work.To fix this problem use the ID from the config only when the config
also provides a name. When no name is provided take the uinque ID of
the nvmem device instead.Signed-off-by: Aban Bedel
Reviewed-by: Moritz Fischer
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
24 Mar, 2017
1 commit
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After the data is read by the secure monitor driver it is being copied
in the output buffer checking only the size of the bounce buffer but not
the size of the output buffer.Fix this in the secure monitor driver slightly changing the API. Fix
also the efuse driver that it is the only driver using this API to not
break bisectability.Signed-off-by: Carlo Caione
Acked-by: Srinivas Kandagatla # for nvmem
Acked-by: Mark Rutland
Signed-off-by: Kevin Hilman
25 Jan, 2017
4 commits
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The nvmem cell with a NULL cell name/id should be the one
with no accompanying 'nvmem-cell-names' property, and thus
will be the cell at index 0 in the device tree.
So, we default to index 0 and update the cell index only when
nvmem cell name id exists.Suggested-by: Stephen Boyd
Signed-off-by: Vivek Gautam
Reviewed-by: Stephen Boyd
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Correct the documentation for arguments to a number
of functions.Signed-off-by: Vivek Gautam
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
nvmem_cell_read() API fills in the argument 'len' with
the number of bytes read from the cell. Many users don't
care about this length value. So allow users to pass a
NULL pointer to this len field.Signed-off-by: Vivek Gautam
Reviewed-by: Stephen Boyd
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
i.MX6UL is an new SOC of i.MX6 family. Enable ocotp
driver support for this SOC.Signed-off-by: Bai Ping
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
05 Jan, 2017
3 commits
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nvmem_cell_read() returns void *, not char *. This is a cleanup that got
left out of commit a6c50912508d ("nvmem: Declare nvmem_cell_read()
consistently").Signed-off-by: Brian Norris
Fixes: a6c50912508d ("nvmem: Declare nvmem_cell_read() consistently")
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
All i.MX6 SoCs have an OCOTP Controller with 4kbit fuses. The i.MX6SL is
an exception and has only 2kbit fuses.In the TRM for the i.MX6DQ (IMX6QDRM - Rev 2, 06/2014) the fuses size is
described in chapter 46.1.1 with:
"32-bit word restricted program and read to 4Kbits of eFuse OTP(512x8)."In the TRM for the i.MX6SL (IMX6SLRM - Rev 2, 06/2015) the fuses size is
described in chapter 34.1.1 with:
"32-bit word restricted program and read to 2 kbit of eFuse OTP(128x8)."Since the Freescale Linux kernel OCOTP driver works with a fuses size of
2 kbit for the i.MX6SL, it looks like the TRM is wrong and the formula
to calculate the correct fuses size has to be 256x8.Signed-off-by: Daniel Schultz
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
The nvmem core driver supports to read and write single
byte. So, allow qfprom to support this feature.
This change helps in extracting a required value based
on bit-offset and number of bits for the required value
in the nvmem cell.Signed-off-by: Vivek Gautam
Cc: Srinivas Kandagatla
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
10 Nov, 2016
2 commits
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Add support for 32 and 64-bit versions of Broadcom's On-Chip OTP
controller. These controllers are used on SoC's such as Cygnus and
Stingray.Reviewed-by: Ray Jui
Tested-by: Jonathan Richardson
Signed-off-by: Scott Branden
Signed-off-by: Oza Pawandeep
Signed-off-by: Jonathan Richardson
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Add simple read only driver for the internal OTP (One Time Programmable)
memory found on all NXP LPC18xx and LPC43xx devices.The OTP memory is split into 4 banks each with 4 32-bits word. Some of
the banks contain predefined data while others are for general purpose
and user programmable via the OTP API in ROM. Note that writing to the
OTP memory is not yet supported.Signed-off-by: Joachim Eastwood
Tested-by: Vladimir Zapolskiy
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman
08 Oct, 2016
1 commit
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Pull ARM SoC driver updates from Arnd Bergmann:
"Driver updates for ARM SoCs, including a couple of newly added
drivers:- The Qualcomm external bus interface 2 (EBI2), used in some of their
mobile phone chips for connecting flash memory, LCD displays or
other peripherals- Secure monitor firmware for Amlogic SoCs, and an NVMEM driver for
the EFUSE based on that firmware interface.- Perf support for the AppliedMicro X-Gene performance monitor unit
- Reset driver for STMicroelectronics STM32
- Reset driver for SocioNext UniPhier SoCs
Aside from these, there are minor updates to SoC-specific bus,
clocksource, firmware, pinctrl, reset, rtc and pmic drivers"* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (50 commits)
bus: qcom-ebi2: depend on HAS_IOMEM
pinctrl: mvebu: orion5x: Generalise mv88f5181l support for 88f5181
clk: mvebu: Add clk support for the orion5x SoC mv88f5181
dt-bindings: EXYNOS: Add Exynos5433 PMU compatible
clocksource: exynos_mct: Add the support for ARM64
perf: xgene: Add APM X-Gene SoC Performance Monitoring Unit driver
Documentation: Add documentation for APM X-Gene SoC PMU DTS binding
MAINTAINERS: Add entry for APM X-Gene SoC PMU driver
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
rtc: rtc-pm8xxx: Add support for pm8018 rtc
nvmem: amlogic: Add Amlogic Meson EFUSE driver
firmware: Amlogic: Add secure monitor driver
soc: qcom: smd: Reset rx tail rather than tx
memory: atmel-sdramc: fix a possible NULL dereference
reset: hi6220: allow to compile test driver on other architectures
reset: zynq: add driver Kconfig option
reset: sunxi: add driver Kconfig option
reset: stm32: add driver Kconfig option
reset: socfpga: add driver Kconfig option
...
02 Sep, 2016
2 commits
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1) the efuse timing of rk3399 is different from earlier SoCs.
2) rk3399-efuse is organized as 32bits by 32 one-time programmable
electrical fuses, the efuse of earlier SoCs is organized as 32bits
by 8 one-time programmable electrical fuses with random access interface.This patch adds a new read function for rk3399-efuse.
Signed-off-by: Finley Xiao
Reviewed-by: Heiko Stuebner
Reviewed-by: Douglas Anderson
Signed-off-by: Srinivas Kandagatla
Signed-off-by: Greg Kroah-Hartman -
Add Amlogic EFUSE driver to access hardware data like ethernet address,
serial number or IDs.Acked-by: Srinivas Kandagatla
Signed-off-by: Carlo Caione
Signed-off-by: Kevin Hilman