03 Nov, 2018
1 commit
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Update SCFW API to the following commit:
"
("430d1e3646fbe75e339e18abf2330565eac906e0")
Author: Chuck Cannon
Date: Fri Nov 2 15:25:45 2018 -0500SCF-105: RN updates.
"Signed-off-by: Ranjani Vaidyanathan
29 Oct, 2018
39 commits
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This needs to be one individual change since otherwise the driver
and the dtbs won't build anymore. This updates all the dts and dtsi files,
the clock index defines and the imx8mq clock driver itselfSigned-off-by: Abel Vesa
Reviewed-by: Leonard Crestez -
The gpmi clock is from NAND clock root, while aphb-dma clock is from NAND_USDHC_BUS_CLK_ROOT.
Both share same clock gate CCGR_NAND. We use imx_clk_gate2_shared2 to
create two clocks for them.Signed-off-by: Ye Li
Reviewed-by: Bai Ping -
Fix PDM input select options, add missing daisy chain
select option for routing PDM bitsream inputs from
SAI1_RXDx pads.Signed-off-by: Adrian Alonso
(cherry picked from commit 8a6f7ddd5ba852fbc4511415506453ba1c575d6a) -
Signed-off-by: Daniel Baluta
Reviewed-by: Shengjiu Wang
(cherry picked from commit 8bc09ad559237c136f88d93bd696fe10dc4658db) -
By default, imx8qm b0 silicon set the IO voltage to 2.5v, but the arm2
board is designed as 1.8v voltage for enet IO, so force the IO voltage
to 1.8 by setting COMP_CTL_GPIO_1V8_3V3 pins like:
For ENET0: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB
For ENET1: SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA
The pin setting:
1.8V/3.3V : bit4=0, bit[30]=1, bit[2:0]=000
2.5V : bit4=1, bit[30]=1, bit[2:0]=010For 2.5v IO timing test, HW board need to do some rework:
- Force PHY work at 2.5v mode
- Supply 1.8v voltage to VDD_ENETxSigned-off-by: Fugang Duan
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In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.Signed-off-by: Richard Zhu
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In the L1.1 ASPM implementation, the CLK_REQ# should be
configured as open drain, pull up and input mode.Signed-off-by: Richard Zhu
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Add SAI1 PDM pin definitions for imx8mm SoC.
Signed-off-by: Adrian Alonso
(cherry picked from commit 1ada53b6b48dc6e7360b75403bd0796b4bf52cf9) -
On i.MX8MM, it has an dram_alt clock source that can be used when
DDRC clock rate is lower than 667MHz, so add this clock.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang
(cherry picked from commit 303867c769e3c0758b9ee8fcf31d8cc3c632a80d) -
Add LCDIF PLL resource and clocks, and power domain for it.
Add Pixel link clocks and set it from bypass path.
Muxes were added so that the slices can choose the bypass input
(lcd_pxl_bypass_div and elcdif_pll_div).clk summary example:
lcd_pxl_bypass_div 2 2 24000000
lcd_pxl_sel 1 1 24000000
lcd_pxl_div 1 1 24000000
lcd_pxl_clk 1 1 24000000
elcdif_pll_div 1 1 792000000
elcdif_pll 2 2 792000000
lcd_sel 1 1 792000000
lcd_div 1 1 79200000
lcd_clk 1 1 79200000Signed-off-by: Adriana Reus
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In order to replace the M4_MU# by the LSIO MU in the
RPMSG usage.
Define the PD and LPCG address of the LSIO MU for iMX8.Signed-off-by: Richard Zhu
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This patch adds the MIPI PWM_DIV and PWM_CLK clock definitions.
The PWM_DIV clock is the parent clock of PWM_CLK clock.
The PWM_CLK will be used as the 'per' clock by the PWM driver.Signed-off-by: Liu Ying
(cherry picked from commit a32d7b4bcca3da7bd154eaf46cf04852279d2c87) -
External differential clock phy_27m can be set to all
plls, rename from VIDEO2_PHY_27M to CLK_PHY_27M to avoid
confusion as clock source is the same option for all pllsSigned-off-by: Adrian Alonso
Reviewed-by: Laurentiu Palcu
(cherry picked from commit e4ac6dff8fa2eda6f5c2ed35cfea3550c59916da) -
add csi clock, CLKO1 for MCLK, and also BUS clock
Signed-off-by: Robby Cai
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Add iMX8MM PDM pins header.
Signed-off-by: Cosmin-Gabriel Samoila
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- mu is used by rpmsg on imx8mm, add the mu root clk.
- check the m4 is enable or not.Signed-off-by: Richard Zhu
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Add hdmi rx clocks define.
Add hdmi rx power domain name.Signed-off-by: Sandor Yu
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fix the gpu2d/3d clock tree on i.MX8MM.
Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
Add i.MX8MM clock definition.
Signed-off-by: Peng Fan
Signed-off-by: Bai Ping
Signed-off-by: Fugang Duan
Signed-off-by: Cosmin-Gabriel Samoila
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Add i.MX8MM pins definition.
Signed-off-by: Bai Ping
Signed-off-by: Peng Fan
Signed-off-by: Haibo Chen
Signed-off-by: Anson Huang
Reviewed-by: Bai Ping -
Ensure that every resource is associated with a power domain
and clocks required.Signed-off-by: Ranjani Vaidyanathan
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In order to avoid the name problem going forward with
integration with Qcom, Qcom has their own dsp and hifi
is competitor, so the hifi name should not be used in
our code.So use the name of dsp instead of hifi to fix this
problem.Signed-off-by: Weiguang Kong
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i.MX8QXP B0 silicon config enet IO voltage as 2.5V setting in default,
but MEK and ARM2 board only support 1.8V IO. So change the IO voltage
as 1.8V setting.Set the MAC RGMII timing as TX no delay and RX delay mode as the default
setting for MEK and ARM2 board.Since i.MX8QXP B0 silicon ENET IO timing change, to reach better timing
and avoid CRC error, MEK base board and ARM2 cpu board should remove the
driver device for the secord enet port.Signed-off-by: Fugang Duan
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Add power domain PD_HDMI_PLL_0/1 and PD_HDMI_I2S.
Signed-off-by: Sandor Yu
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Add power domain macro names for CI_PI subsystem.
Reviewed-by: Sandor.Yu
Signed-off-by: Guoniu.Zhou
(cherry picked from commit fd8318f4455ceafda963681ce05effd0ad81d714) -
Register clocks for CI_PI subsystem.
Reviewed-by: Sandor.Yu
Signed-off-by: Guoniu.Zhou
(cherry picked from commit d29308ec4fa29addd049c114520d7628e9e921d7) -
Some resources are being enabled without the associated resource being
powered up.Signed-off-by: Oliver Brown
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Signed-off-by: Laurentiu Palcu
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Add missing sosc_bus_clk/firc_bus_clk/spll_bus_clk clocks which will be used
by other devices later.All these clocks use the same divider as ddr_div, so ulp_div_table is used.
Besides that, all these clocks need to be controlled by M4, so
CLK_DIVIDER_READ_ONLY is also specified.Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang
Reviewed-by: Bai Ping
Signed-off-by: Dong Aisheng -
'CKIL' clock name is derived from MX6 SoC series which is invalid for
MX7ULP (can't find it from RM). Changing it to the correct 'ROSC'
which is defined in RM.The exist 'OSC' name is also changed accordingly which should be SOSC
(System OSC).Fixes: aacf0b70af26 ("MLK-13441-6 ARM: imx: add i.mx7ulp clock driver")
Cc: Anson Huang
Reviewed-by: Bai Ping
Signed-off-by: Dong Aisheng -
Define hdmi pixel select clocks.
Define av_pll_bypass clock.Signed-off-by: Sandor Yu
Reviewed-by: Robby Cai -
Rename imx8x mipi csi i2c power domain.
Acked-by: Fugang Duan
Signed-off-by: Sandor Yu -
The CCGR RAWNAND is shared by apbh-dma and gpmi clocks, so must use
imx_clk_gate2_shared2 to produce two clocks. Otherwise, apbh-dma clock
won't be enabled individually.Signed-off-by: Ye Li
Reviewed-by: Bai Ping -
Add uSDHC clock MUX to allow uSDHC driver to select
parent, currently only support PLL0 and PLL1 as
uSDHC clock's parent.Signed-off-by: Anson Huang
Reviewed-by: Bai Ping
Tested-by: Haibo Chen -
This patch adds IMX8QXP_DC0_DPR1_APB_CLK and IMX8QXP_DC0_DPR1_B_CLK clocks
support.Signed-off-by: Liu Ying
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Add CLKO2 for i.MX8MQ
Set parent for MIPI CSI1/2 CORE/PHY_REF/ESCSigned-off-by: Robby Cai
Reviewed-by: Sandor Yu -
The Video PLL2 has a output enable bit to do clk gate,
So we need to register this gate to save power.Signed-off-by: Bai Ping
Reviewed-by: Anson Huang -
Add missing clocks for MIPI-DSI SS: RX_ESC and TX_ESC
Also added the posibility to select clock parents for MIPI-DSI versus
LVDS.
The SCFW was changed, so now the LVDS pixel and phy clocks need to
specify their parrents.
Also, the TX_ESC and RX_ESC clocks from MIPI-DSI need to specify their
parrents in DTS files.Signed-off-by: Robert Chiras
Signed-off-by: Oliver Brown -
add the mu clock
Signed-off-by: Richard Zhu
