09 Mar, 2010
40 commits
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Signed-off-by: Harald Krapfenbauer
Signed-off-by: Mike Frysinger -
When the kernel is executing out of parallel flash (XIP), we can't have
the flash go into an erase/programming cycle, otherwise the instruction
fetching steps fail and everything crashes.Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Signed-off-by: Cliff Cai
Signed-off-by: Mike Frysinger -
The locking code in the address dumper needs to grab the mm's mmap_sem
so that other CPUs do not get an inconsistent view. On UP systems this
really wasn't a problem, but it is easy to trigger a race on SMP systems
when another CPU removes a mapping.Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger -
Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Signed-off-by: Mike Frysinger
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This condition allowed only decoding of opcode 0x0040
Signed-off-by: Roel Kluin
Signed-off-by: Mike Frysinger -
Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
During very early init, the stack pointer is given a slightly incorrect
value (&init_thread_union). The value is later adjusted to the right one
during early init (&init_thread_union + THREAD_SIZE), but it is used a few
times in between. While the few functions used don't actually put things
onto the stack (due to optimization), it's best if we simply use the right
value from the start.Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Use the common attribute rather than setting the section name directly.
The common linker script defines expect the newer naming.Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Since we are now discarding .exit.text at runtime instead of link time, we
need to place all .text sections ahead of the .data sections. Otherwise,
a really large attached initramfs may cause link errors as it pushes the
PC relative relocations behind the limits of the Blackfin ISA (~16meg).
The instructions in the .exit.text are unable to call back into the .text
sections leading to a link failure.Signed-off-by: Jie Zhang
Signed-off-by: Mike Frysinger -
Signed-off-by: Yi Li
Signed-off-by: Mike Frysinger -
There is no need to use {get,put}_cpu() when we already have a spinlock to
protect against multiple processors running simultaneously.Signed-off-by: Yi Li
Signed-off-by: Mike Frysinger -
Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger -
SMP systems require per-cpu local clock event devices in order to enable
HRT support. One a BF561, we can use local core timer for this purpose.
Originally, there was one global core-timer clock event device set up for
core A.To accomplish this feat, we need to split the gptimer0/core timer logic
so that each is a standalone clock event. There is no requirement that
we only have one clock event source anyways. Once we have this, we just
define per-cpu clock event devices for each local core timer.Signed-off-by: Yi Li
Signed-off-by: Mike Frysinger -
Common API already provides functions for managing online CPUs.
Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger -
Now that the Blackfin IRQ controller supports this, drivers get the normal
functionality of controlling which CPU to bind IRQs to.Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger -
Signed-off-by: Mike Frysinger
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Don't want the compiler assuming the rare sanity checks are the norm and
optimize for those paths.Signed-off-by: Mike Frysinger
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Signed-off-by: Sonic Zhang
Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Signed-off-by: Valentin Yakovenkov
Signed-off-by: Mike Frysinger -
Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger -
The Kconfig option was never mainlined, so replace the define with the
actual pin that it is hooked up to by default.Signed-off-by: Mike Frysinger
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These platforms don't hook up to this USB controller, so no point in
declaring resources for it.Signed-off-by: Mike Frysinger
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The BF51x's Instruction SRAM is 32kB, not 48kB.
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
The gpio label size is 16 char, but the current code uses a longer name
resulting in chopped display. So use a shorter name.Reported-by: Peter Meerwald
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Make sure the non-constant version of the dma_sync functions actually
complete instead of recursively calling itself forever.Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger -
The option already exists for everyone in init/Kconfig.
Signed-off-by: Mike Frysinger
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Rather than copy and paste the MMR defines and register layout,
consolidate everything in one place.Signed-off-by: Mike Frysinger
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These all just go to the stub syscall at the moment, so this is largely
future proofing.Signed-off-by: Mike Frysinger
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The current Blackfin SMP code relies on the legacy cpu area code, so
select it until we port things to the newer code.Signed-off-by: Graf Yang
Signed-off-by: Mike Frysinger -
We weren't handling the user-specified cache behavior for the reserved
memory regions (via mem=/max_mem=). The no-MPU code already takes care
of this, so add support to the MPU code as well.Signed-off-by: Sonic Zhang
Signed-off-by: Mike Frysinger -
This lets us support the new BF527-EZKIT V2.1 via platform resources
tweaks only.Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Signed-off-by: Michael Hennerich
Signed-off-by: Mike Frysinger -
Attempting to use the MPU while doing XIP out of parallel flash hooked up
to the async memory bus would often result in random crashes as the MPU
slowly corrupted memory.The fallout here is that the async banks gain MPU protection from user
space too. So any accesses have to go through the mmap() interface rather
than just using hardcoded pointers.Signed-off-by: Barry Song
Signed-off-by: Mike Frysinger -
Sometimes a SMP system will randomly panic at boot. This is due to caches
being out of sync when one core tries to signal the other. So when one
core calls another via IPI, flush the data caches.Signed-off-by: Yi Li
Signed-off-by: Mike Frysinger