05 Jan, 2012
1 commit
-
Conflicts:
arch/arm/kernel/setup.c
arch/arm/mach-shmobile/board-kota2.c
04 Jan, 2012
1 commit
03 Jan, 2012
1 commit
-
This reverts commit 0af362f8440a78b970d5f215e234420fa87d0f3f as shmobile
is not using a non-standard memory layout anymore.Signed-off-by: Nicolas Pitre
09 Dec, 2011
1 commit
-
…/linux into devel-stable
Conflicts:
arch/arm/mm/ioremap.c
08 Dec, 2011
3 commits
-
This patch introduces the pgtable-3level*.h files with definitions
specific to the LPAE page table format (3 levels of page tables).Each table is 4KB and has 512 64-bit entries. An entry can point to a
40-bit physical address. The young, write and exec software bits share
the corresponding hardware bits (negated). Other software bits use spare
bits in the PTE.The patch also changes some variable types from unsigned long or int to
pteval_t or pgprot_t.Signed-off-by: Catalin Marinas
-
The page table maintenance macros need to be duplicated between the
classic and the LPAE MMU so this patch moves those that are not common
to the pgtable-2level.h file.Signed-off-by: Catalin Marinas
-
Nick Piggin noted upon introducing 4level-fixup.h:
| Add a temporary "fallback" header so architectures can run with
| the 4level pagetables patch without modification. All architectures
| should be converted to use the folding headers (include/asm-generic/
| pgtable-nop?d.h) as soon as possible, and the fallback header removed.This makes ARM compliant with this statement.
Signed-off-by: Russell King
Signed-off-by: Catalin Marinas
07 Dec, 2011
1 commit
-
…/linux into devel-stable
06 Dec, 2011
2 commits
-
When disabling and re-enabling the MMU, it is necessary to take out an
identity mapping for the code that manipulates the SCTLR in order to
avoid it disappearing from under our feet. This is useful when soft
rebooting and returning from CPU suspend.This patch allocates a set of page tables during boot and populates them
with an identity mapping for the .idmap.text section. This means that
users of the identity map do not need to manage their own pgd and can
instead annotate their functions with __idmap or, in the case of assembly
code, place them in the correct section.Acked-by: Dave Martin
Reviewed-by: Catalin Marinas
Tested-by: Lorenzo Pieralisi
Signed-off-by: Will Deacon -
Similar to other architectures, this adds topdown mmap support in user
process address space allocation policy. This allows mmap sizes greater
than 2GB. This support is largely copied from MIPS and the generic
implementations.The address space randomization is moved into arch_pick_mmap_layout.
Tested on V-Express with ubuntu and a mmap test from here:
https://bugs.launchpad.net/bugs/861296Signed-off-by: Rob Herring
Acked-by: Nicolas Pitre
Signed-off-by: Russell King
27 Nov, 2011
2 commits
-
THIS IS A TEMPORARY HACK. The purpose of this is _only_ to avoid a
regression on an existing machine while a better fix is implemented.On shmobile the consistent DMA memory area was set to 158MB in commit
28f0721a79 with no explanation. The documented size for this area should
vary between 2MB and 14MB, and none of the other ARM targets exceed that.The included #warning is therefore meant to be noisy on purpose to get
shmobile maintainers attention and this commit reverted once this
consistent DMA size conflict is resolved.Signed-off-by: Nicolas Pitre
Cc: Magnus Damm
Cc: Paul Mundt -
In order to remove the build time variation between different SOCs with
regards to VMALLOC_END, the iotable mappings are now allocated inside
the vmalloc region. This allows for VMALLOC_END to be identical across
all machines.The value for VMALLOC_END is now set to 0xff000000 which is right where
the consistent DMA area starts.To accommodate all static mappings on machines with possible highmem usage,
the default vmalloc area size is changed to 240 MB so that VMALLOC_START
is no higher than 0xf0000000 by default.Signed-off-by: Nicolas Pitre
Tested-by: Stephen Warren
Tested-by: Kevin Hilman
Tested-by: Jamie Iles
29 Oct, 2011
1 commit
-
…git-cur/linux-2.6-arm
* 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (178 commits)
ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET
ARM: gic, local timers: use the request_percpu_irq() interface
ARM: gic: consolidate PPI handling
ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H
ARM: mach-s5p64x0: remove mach/memory.h
ARM: mach-s3c64xx: remove mach/memory.h
ARM: plat-mxc: remove mach/memory.h
ARM: mach-prima2: remove mach/memory.h
ARM: mach-zynq: remove mach/memory.h
ARM: mach-bcmring: remove mach/memory.h
ARM: mach-davinci: remove mach/memory.h
ARM: mach-pxa: remove mach/memory.h
ARM: mach-ixp4xx: remove mach/memory.h
ARM: mach-h720x: remove mach/memory.h
ARM: mach-vt8500: remove mach/memory.h
ARM: mach-s5pc100: remove mach/memory.h
ARM: mach-tegra: remove mach/memory.h
ARM: plat-tcc: remove mach/memory.h
ARM: mach-mmp: remove mach/memory.h
ARM: mach-cns3xxx: remove mach/memory.h
...Fix up mostly pretty trivial conflicts in:
- arch/arm/Kconfig
- arch/arm/include/asm/localtimer.h
- arch/arm/kernel/Makefile
- arch/arm/mach-shmobile/board-ap4evb.c
- arch/arm/mach-u300/core.c
- arch/arm/mm/dma-mapping.c
- arch/arm/mm/proc-v7.S
- arch/arm/plat-omap/Kconfig
largely due to some CONFIG option renaming (ie CONFIG_PM_SLEEP ->
CONFIG_ARM_CPU_SUSPEND for the arm-specific suspend code etc) and
addition of NEED_MACH_MEMORY_H next to HAVE_IDE.
06 Oct, 2011
2 commits
-
With LPAE, the physical address mask is 40-bit while the page table
entry is 64-bit. This patch introduces PHYS_MASK for the 2-level page
table format, defined as ~0UL.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
This patch moves page table definitions from asm/page.h, asm/pgtable.h
and asm/ptgable-hwdef.h into corresponding *-2level* files.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
23 Sep, 2011
1 commit
-
On certain architectures, there might be a need to mark certain
addresses with strongly ordered memory attributes to avoid ordering
issues at the interconnect level.On OMAP4, the asynchronous bridge buffers can only be drained
with strongly ordered accesses and hence the need to mark the
memory strongly ordered.Signed-off-by: Santosh Shilimkar
Signed-off-by: Woodruff Richard
Tested-by: Vishwanath BS
22 Feb, 2011
1 commit
-
Add pud_offset() et.al. between the pgd and pmd code in preparation of
using pgtable-nopud.h rather than 4level-fixup.h.This incorporates a fix from Jamie Iles for
uaccess_with_memcpy.c.Signed-off-by: Russell King
15 Feb, 2011
1 commit
-
The unsigned long datatype is not sufficient for mapping physical addresses
>= 4GB.This patch ensures that the phys_addr_t datatype is used to represent physical
addresses when converting from a PFN.Acked-by: Catalin Marinas
Signed-off-by: Will Deacon
Signed-off-by: Russell King
22 Dec, 2010
5 commits
-
Signed-off-by: Russell King
-
The hardware page tables use an XN bit 'execute never'. Historically,
we've had a Linux 'execute allow' bit, in the positive sense. Get rid
of this artifact as future hardware will continue to have the XN sense.Signed-off-by: Russell King
-
FIRST_USER_PGD_NR is now unnecessary, as this has been replaced by
FIRST_USER_ADDRESS except in the architecture code. Fix up the last
usage of FIRST_USER_PGD_NR, and remove the definition.Signed-off-by: Russell King
-
We have two places where we create identity mappings - one when we bring
secondary CPUs online, and one where we setup some mappings for soft-
reboot. Combine these two into a single implementation. Also collect
the identity mapping deletion function.Signed-off-by: Russell King
-
This switches the ordering of the Linux vs hardware page tables in
each page, thereby eliminating some of the arithmetic in the page
table walks. As we now place the Linux page table at the beginning
of the page, we can deal with the offset in the pgt by simply masking
it away, along with the other control bits.This also makes the arithmetic all be positive, rather than a mixture.
Signed-off-by: Russell King
27 Nov, 2010
6 commits
-
This makes everywhere dealing with pte values use the same type.
Signed-off-by: Russell King
-
Ensure that physical addresses are typed as phys_addr_t
Signed-off-by: Russell King
-
Rather than passing the pte value to __pte_error, pass the raw pte_t
cookie instead. Do the same for pmd and pgd functions.Signed-off-by: Russell King
-
Signed-off-by: Russell King
-
Signed-off-by: Russell King
-
Rather than scattering them throughout the file, group them together.
Signed-off-by: Russell King
21 Nov, 2010
1 commit
-
Allow the compiler to better optimize the page table walking code
by avoiding over-complex pmd_addr_end() calculations. These
calculations prevent the compiler spotting that we'll never iterate
over the PMD table, causing it to create double nested loops where
a single loop will do.Signed-off-by: Russell King
27 Oct, 2010
1 commit
-
Since we no longer need to provide KM_type, the whole pte_*map_nested()
API is now redundant, remove it.Signed-off-by: Peter Zijlstra
Acked-by: Chris Metcalf
Cc: David Howells
Cc: Hugh Dickins
Cc: Rik van Riel
Cc: Ingo Molnar
Cc: Thomas Gleixner
Cc: "H. Peter Anvin"
Cc: Steven Rostedt
Cc: Russell King
Cc: Ralf Baechle
Cc: David Miller
Cc: Paul Mackerras
Cc: Benjamin Herrenschmidt
Signed-off-by: Andrew Morton
Signed-off-by: Linus Torvalds
19 Oct, 2010
1 commit
-
…x' and 'unwind' into devel
19 Sep, 2010
2 commits
-
ARMv7 onwards requires that there are no aliases to the same physical
location using different memory types (i.e. Normal vs Strongly Ordered).
Access to SO mappings when the unaligned accesses are handled in
hardware is also Unpredictable (pgprot_noncached() mappings in user
space).The /dev/mem driver requires uncached mappings with O_SYNC. The patch
implements the phys_mem_access_prot() function which generates Strongly
Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and
Normal Noncacheable (writecombine) if O_SYNC.Signed-off-by: Catalin Marinas
Signed-off-by: Russell King -
On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the current cache maintenance operations in
update_mmu_cache(). To avoid this, cache maintenance must be handled in
set_pte_at() (similar to IA-64 and PowerPC).This patch provides a unified VIPT cache handling mechanism and
implements the __sync_icache_dcache() function for ARMv6 onwards
architectures. It is called from set_pte_at() and replaces the
update_mmu_cache(). The latter is still used on VIVT hardware where a
vm_area_struct is required.Tested-by: Rabin Vincent
Cc: Nicolas Pitre
Signed-off-by: Catalin Marinas
Signed-off-by: Russell King
17 May, 2010
1 commit
-
Provide a configuration option to allow the ARMv6 to use normal
bufferable memory for coherent DMA. This option is forced to 'y'
for ARMv7, and offered as a configuration option on ARMv6.Enabling this option requires drivers to have the necessary barriers
to ensure that data in DMA coherent memory is visible prior to the
DMA operation commencing.Reviewed-by: Catalin Marinas
Signed-off-by: Russell King
25 Nov, 2009
1 commit
-
On ARMv7, it is invalid to map the same physical address multiple times
with different memory types. Since system RAM is already mapped as
'memory', subsequent remapping of it must retain this attribute.However, DMA memory maps it as "strongly ordered". Fix this by introducing
'pgprot_dmacoherent()' which provides the necessary page table bits for
DMA mappings.Signed-off-by: Russell King
Acked-by: Greg Ungerer
Reviewed-by: Catalin Marinas
18 Aug, 2009
1 commit
-
Add the ARM implementation of highpte, which allows PTE tables to be
placed in highmem. Unfortunately, we do not offer highpte support
when support for L2 cache is enabled.Signed-off-by: Russell King
11 Jul, 2009
2 commits
-
For future compatibility, we need to ensure that swap and file Linux
PTEs conform with the hardware PTEs "fault" encoding. Swap PTEs
already fit in with this, but file PTEs do not. Shift them by one
bit to ensure that they conform, using bit 2 to distinguish between
swap and file PTEs.Signed-off-by: Russell King
-
These old symbols are meaningless now that we have memory type
support implemented. The entire memory type field needs to be
modified rather than just a few bits twiddled.Signed-off-by: Russell King
05 Jul, 2009
1 commit
-
Document the layout of our file PTE entries.
Signed-off-by: Russell King