Eric Lee / smarc-fsl-linux-kernel

25 May, 2011

1 commit

  • aecb7b64d   dmaengine/dw_dmac: Update maintainer-ship ... Browse Code »

    Nobody is currently maintaining dw_dmac. We are using dw_dmac for SPEAr13xx and
    are currently maintaining it. After discussing with Vinod, sending this patch to
    update maintainer-ship of dw_dmac.

    Signed-off-by: Viresh Kumar
    Acked-by: Havard Skinnemoen
    Signed-off-by: Vinod Koul

    Viresh Kumar
     

13 May, 2011

1 commit

07 Mar, 2011

3 commits

  • 29782da5f   dmaengine/dw_dmac fix: use readl & writel instead of __raw_readl & __raw_writel ... Browse Code »

    On ARMv7 cores, device memory mapped as Normal Non-cacheable, may not guarantee
    ordered access causing failures in device drivers that do not use the mandatory
    memory barriers. readl & writel versions contain necessary memory barriers for
    this.

    commit 79f64dbf68c8a9779a7e9a25e0a9f0217a25b57a: "ARM: 6273/1: Add barriers to
    the I/O accessors if ARM_DMA_MEM_BUFFERABLE" can be referred for more
    information on this.

    Signed-off-by: Viresh Kumar
    Signed-off-by: Vinod Koul

    Viresh Kumar
     
  • ee66509d7   dw_dmac: Allow src/dst msize & flow controller to be configured at runtime ... Browse Code »

    Msize or Burst Size is peripheral dependent in case of prep_slave_sg and
    cyclic_prep transfers, and in case of memcpy transfers it is platform dependent.
    So msize configuration must come from platform data.

    Also some peripherals (ex: JPEG), need to be flow controller for dma transfers,
    so this information in case of slave_sg & cyclic_prep transfers must come from
    platform data.

    Signed-off-by: Viresh Kumar
    Signed-off-by: Vinod Koul

    Viresh KUMAR
     
  • 93317e8e3   dw_dmac: Pass Channel Priority from platform_data ... Browse Code »

    In Synopsys designware, channel priority is programmable. This patch adds
    support for passing channel priority through platform data. By default Ascending
    channel priority will be followed, i.e. channel 0 will get highest priority and
    channel 7 will get lowest.

    Signed-off-by: Viresh Kumar
    Signed-off-by: Vinod Koul

    Viresh Kumar
     

09 Sep, 2009

1 commit

02 Apr, 2009

1 commit

  • d9de45198   dw_dmac: add cyclic API to DW DMA driver ... Browse Code »

    This patch adds a cyclic DMA interface to the DW DMA driver. This is
    very useful if you want to use the DMA controller in combination with a
    sound device which uses cyclic buffers.

    Using a DMA channel for cyclic DMA will disable the possibility to use
    it as a normal DMA engine until the user calls the cyclic free function
    on the DMA channel. Also a cyclic DMA list can not be prepared if the
    channel is already active.

    Signed-off-by: Hans-Christian Egtvedt
    Acked-by: Haavard Skinnemoen
    Acked-by: Maciej Sosnowski
    Signed-off-by: Dan Williams

    Hans-Christian Egtvedt
     

19 Feb, 2009

1 commit

  • 287d85922   atmel-mci: fix initialization of dma slave data ... Browse Code »

    The conversion of atmel-mci to dma_request_channel missed the
    initialization of the channel dma_slave information. The filter_fn passed
    to dma_request_channel is responsible for initializing the channel's
    private data. This implementation has the additional benefit of enabling
    a generic client-channel data passing mechanism.

    Reviewed-by: Atsushi Nemoto
    Signed-off-by: Dan Williams
    Acked-by: Haavard Skinnemoen
    Signed-off-by: Andrew Morton
    Signed-off-by: Linus Torvalds

    Dan Williams
     

09 Jul, 2008

1 commit

  • 3bfb1d20b   dmaengine: Driver for the Synopsys DesignWare DMA controller ... Browse Code »

    This adds a driver for the Synopsys DesignWare DMA controller (aka
    DMACA on AVR32 systems.) This DMA controller can be found integrated
    on the AT32AP7000 chip and is primarily meant for peripheral DMA
    transfer, but can also be used for memory-to-memory transfers.

    This patch is based on a driver from David Brownell which was based on
    an older version of the DMA Engine framework. It also implements the
    proposed extensions to the DMA Engine API for slave DMA operations.

    The dmatest client shows no problems, but there may still be room for
    improvement performance-wise. DMA slave transfer performance is
    definitely "good enough"; reading 100 MiB from an SD card running at ~20
    MHz yields ~7.2 MiB/s average transfer rate.

    Full documentation for this controller can be found in the Synopsys
    DW AHB DMAC Databook:

    http://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf

    The controller has lots of implementation options, so it's usually a
    good idea to check the data sheet of the chip it's intergrated on as
    well. The AT32AP7000 data sheet can be found here:

    http://www.atmel.com/dyn/products/datasheets.asp?family_id=682

    Changes since v4:
    * Use client_count instead of dma_chan_is_in_use()
    * Add missing include
    * Unmap buffers unless client told us not to

    Changes since v3:
    * Update to latest DMA engine and DMA slave APIs
    * Embed the hw descriptor into the sw descriptor
    * Clean up and update MODULE_DESCRIPTION, copyright date, etc.

    Changes since v2:
    * Dequeue all pending transfers in terminate_all()
    * Rename dw_dmac.h -> dw_dmac_regs.h
    * Define and use controller-specific dma_slave data
    * Fix up a few outdated comments
    * Define hardware registers as structs (doesn't generate better
    code, unfortunately, but it looks nicer.)
    * Get number of channels from platform_data instead of hardcoding it
    based on CONFIG_WHATEVER_CPU.
    * Give slave clients exclusive access to the channel

    Acked-by: Maciej Sosnowski ,
    Signed-off-by: Haavard Skinnemoen
    Signed-off-by: Dan Williams

    Haavard Skinnemoen