06 Oct, 2011
3 commits
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Sparse complains that edac_cap was declared as dev_type and we are
returning edac_type. Historically, edac_type was correct but since
then we have changed it to return a bit field.Signed-off-by: Dan Carpenter
Link: http://lkml.kernel.org/r/20111006063025.GA2615@mwanda
Signed-off-by: Borislav Petkov -
When accessing the scrub rate control register (F3x58) on F15h, the DRAM
controller selector (F1x10C[DctCfgSel]) has to point to DCT0 so that the
scrub rate configuration can take effect. See Erratum 505 in the AMD
F15h revision guide for more details.Signed-off-by: Borislav Petkov
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Drop third nbcfg argument which is old remains and not required anymore.
No functionality change.
Signed-off-by: Borislav Petkov
26 Apr, 2011
3 commits
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F15h CPUs may report a non-DRAM address when reporting an error address
belonging to a CC6 state save area. Add a workaround to detect this
condition and compute the actual DRAM address of the error as documented
in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors.Signed-off-by: Borislav Petkov
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F15h and later use a portion of DRAM as a CC6 storage area. BIOS
programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by
subtracting the storage area from the DRAM limit setting. However, in
order for edac to consider that part of DRAM too, we need to include it
into the per-node range.Signed-off-by: Borislav Petkov
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This warning was wrongfully added for a normal condition - intlvsel
actually selects the destination node when node interleaving is enabled
and it is not a mismatch. For a detailed example, see section 2.8.10.2
"Node Interleaving" in F10h BKDG.Signed-off-by: Borislav Petkov
21 Apr, 2011
1 commit
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This patch removes superfluous debugging output in the sysfs scrub rate
handler. It also consolidates the error handling in the scrub rate
accessors.Signed-off-by: Markus Trippelsdorf
Signed-off-by: Borislav Petkov
30 Mar, 2011
1 commit
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We check the pointers together but at least one of them could be invalid
due to failed allocation. Since we cannot continue if either of the two
allocations has failed, exit early by freeing them both.Cc: # 38.x
Reported-by: Mauro Carvalho Chehab
Signed-off-by: Borislav Petkov
17 Mar, 2011
32 commits
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Those should all be unsigned.
Signed-off-by: Borislav Petkov
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Fix amd64_debug_display_dimm_sizes() arguments order per convention (pvt
is always first). Also, the now second arg denotes the DCT so adjust its
type.Signed-off-by: Borislav Petkov
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The dram ranges make sense only as an unsigned type.
Signed-off-by: Borislav Petkov
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Use the macro directly instead
Signed-off-by: Borislav Petkov
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Adjust argument types to the PCI config API's types.
Signed-off-by: Borislav Petkov
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Return unsigned u8 values only.
Signed-off-by: Borislav Petkov
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A node id can never be negative since we use it as an index into
the DRAM ranges array. This also makes one of the BUG_ON conditions
redundant.Signed-off-by: Borislav Petkov
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Add the PCI device ids required for driver registration. Remove
pvt->ctl_name and use the family descriptor directly, instead. Then,
bump driver version and fixup its format. Finally, enable DRAM ECC
decoding on F15h.Signed-off-by: Borislav Petkov
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F15h has the same ECC symbol size options as F10h revD and later so
adjust checks to that. Simplify code a bit.Signed-off-by: Borislav Petkov
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Drop per-instance variable and compute min scrubrate dynamically.
Signed-off-by: Borislav Petkov
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Drop static tables which map the bits in F2x80 to a chip select size in
favor of functions doing the mapping with some bit fiddling. Also, add
F15 support.Signed-off-by: Borislav Petkov
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This function is relevant for F10h and higher, and it has only one
callsite so drop its function pointer from the low_ops struct.Signed-off-by: Borislav Petkov
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F15h sys_addr to chip select mapping is almost identical to F10h's so
reuse that. Rename functions on that path accordingly.Signed-off-by: Borislav Petkov
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Add paranoid checks for the sys address before going off and decoding
it.Signed-off-by: Borislav Petkov
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Replace per-DCT macros with smarter ones, drop hack and look for the
spare rank on all chip selects on a channel.Signed-off-by: Borislav Petkov
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Remove the channel interleave select bit properly. See
F2x110[DctSelIntLvAddr] for details.Signed-off-by: Borislav Petkov
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When node interleaving is enabled, a subset of the addr[14:12] bits has
to be removed in order to get the normalized DCT address of the DRAM
channel. The actual number of bits to remove is determined by F1x[1,
0][7C:40][IntlvEn]. Do this correctly.Signed-off-by: Borislav Petkov
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On revC3 and revE Fam10h machines and later, non-interleaved graphics
framebuffer memory under the 16G mark can be swapped with a region
located at the bottom of memory so that the GPU can use the interleaved
region and thus two channels. Add support for that.Signed-off-by: Borislav Petkov
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The address bits from MC4_STATUS differ only between K8 and the rest so
no need for a per-family method.No functional change.
Signed-off-by: Borislav Petkov
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Use the struct mce directly instead of copying from it into a custom
struct err_regs.No functionality change.
Signed-off-by: Borislav Petkov
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The only difference is that F10h used to sport ganged DCTs and F15h
doesn't so adjust the F10h routine and reuse it.Signed-off-by: Borislav Petkov
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Remove unused defines, drop family names from define names.
Signed-off-by: Borislav Petkov
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Remove reporting of errors with UC bit set - this is done by the MCE
decoding code anyway and this driver deals with DRAM ECC errors only. UC
(NB uncorrectable error) doesn't necessarily mean it is a DRAM error.
Remove unused macros while at it.Signed-off-by: Borislav Petkov
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The fact whether we are chipkill capable or not does not have any
bearing when computing the channel index on a ganged DCT configuration
so remove that. Also, simplify debug statements. Finally, remove old
error injection leftovers, while at it.Signed-off-by: Borislav Petkov
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Remove family names from macro names, drop single bit defines and
comment their meaning instead.No functional change.
Signed-off-by: Borislav Petkov
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Shorten macro names, remove family name from macros, fix macro
arguments, shorten debug strings.No functionality change.
Signed-off-by: Borislav Petkov
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* Restrict DCT ganged mode check since only Fam10h supports it
* Adjust DRAM type detection for BD since it only supports DDR3
* Remove second and thus unneeded DCLR read in k8_early_channel_count() - we do
that in read_mc_regs()
* Cleanup comments and remove family names from register macros
* Remove unused definesThere should be no functional change resulting from this patch.
Signed-off-by: Borislav Petkov
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Do not read DBAM regs twice and simplify code around them.
There should be no functional change resulting from this patch.
Signed-off-by: Borislav Petkov
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Replace hard to read hex constants with a continuous masks macro.
Signed-off-by: Borislav Petkov
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This function maps the system address to the normalized DCT address.
Document what the code does for more clarity and wrap insane bitmasks in
a more understandable macro which generates them. Also, reduce number of
arguments passed to the function. Finally, rename this function to what
it actually does.No functional change.
Signed-off-by: Borislav Petkov
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Cleanup and simplify f10_determine_channel(); make it more readable.
Also drop f10_map_intlv_en_to_shift() in favor of simply counting the
bits in F1x124[DramIntlvEn] which is equivalent.There should be no functionality change resulting from this patch.
Signed-off-by: Borislav Petkov
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Add a struct representing the DRAM chip select base/limit register
pairs. Concentrate all CS handling in a single function. Also, add CS
looping macros for cleaner, more readable code. While at it, adjust code
to F15h. Finally, do smaller macro names cleanups (remove family names
from register macros) and debug messages clarification.No functional change.
Signed-off-by: Borislav Petkov