17 Mar, 2011

1 commit

  • F15h "multiplexes" between the configuration space of the two DRAM
    controllers by toggling D18F1x10C[DctCfgSel] while F10h has a different
    set of registers for DCT0, and DCT1 in extended PCI config space.

    Add DCT configuration space accessors per family thus wrapping all the
    different access prerequisites. Clean up code while at it, shorten
    names.

    Signed-off-by: Borislav Petkov

    Borislav Petkov
     

07 Jan, 2011

2 commits


07 Oct, 2009

1 commit

  • When injecting DRAM ECC errors (F3xBC_x8), EccVector[15:0] is a bitmask
    of which bits should be error injected when written to and holds the
    payload of 16-bit DRAM word when read, respectively.

    Add /sysfs members to show the DRAM ECC section/word/vector.

    Fail wrong injection values entered over /sysfs instead of truncating
    them.

    Signed-off-by: Borislav Petkov

    Borislav Petkov
     

10 Jun, 2009

1 commit